From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 20 May 2020 05:00:47 +0000 (+0100)
Subject: minor code-munge, use shorter names
X-Git-Tag: div_pipeline~1049
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9905c00cc0cbc81075138a5dedbd7aeab3a24239;p=soc.git

minor code-munge, use shorter names
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 4a3785ef..862c5ea3 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -402,8 +402,8 @@ class PowerDecode2(Elaboratable):
         # decoded/selected instruction flags
         comb += self.e.invert_a.eq(self.dec.op.inv_a)
         comb += self.e.invert_out.eq(self.dec.op.inv_out)
-        comb += self.e.input_carry.eq(self.dec.op.cry_in)
-        comb += self.e.output_carry.eq(self.dec.op.cry_out)
+        comb += self.e.input_carry.eq(self.dec.op.cry_in)   # carry comes in
+        comb += self.e.output_carry.eq(self.dec.op.cry_out) # carry goes out
         comb += self.e.is_32bit.eq(self.dec.op.is_32b)
         comb += self.e.is_signed.eq(self.dec.op.sgn)
         with m.If(self.dec.op.lk):
@@ -411,10 +411,10 @@ class PowerDecode2(Elaboratable):
 
         comb += self.e.byte_reverse.eq(self.dec.op.br)
         comb += self.e.sign_extend.eq(self.dec.op.sgn_ext)
-        comb += self.e.update.eq(self.dec.op.upd)
+        comb += self.e.update.eq(self.dec.op.upd) # LD/ST "update" mode
 
-        comb += self.e.input_cr.eq(self.dec.op.cr_in)
-        comb += self.e.output_cr.eq(self.dec.op.cr_out)
+        comb += self.e.input_cr.eq(self.dec.op.cr_in)   # condition reg comes in
+        comb += self.e.output_cr.eq(self.dec.op.cr_out) # condition reg goes in
 
 
         return m
diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index 2457a750..e088caf9 100644
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -23,29 +23,30 @@ class ALUMainStage(PipeModBase):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
-        carry_out, o = self.o.xer_co, self.o.o
+        carry_out, o, cr0 = self.o.xer_co, self.o.o, self.o.cr0
+        a, b, op = self.i.a, self.i.b, self.i.ctx.op
 
         # check if op is 32-bit, and get sign bit from operand a
         is_32bit = Signal(reset_less=True)
         sign_bit = Signal(reset_less=True)
-        comb += is_32bit.eq(self.i.ctx.op.is_32bit)
-        comb += sign_bit.eq(Mux(is_32bit, self.i.a[31], self.i.a[63]))
+        comb += is_32bit.eq(op.is_32bit)
+        comb += sign_bit.eq(Mux(is_32bit, a[31], a[63]))
 
         # little trick: do the add using only one add (not 2)
-        add_a = Signal(self.i.a.width + 2, reset_less=True)
-        add_b = Signal(self.i.a.width + 2, reset_less=True)
-        add_output = Signal(self.i.a.width + 2, reset_less=True)
-        with m.If((self.i.ctx.op.insn_type == InternalOp.OP_ADD) |
-                  (self.i.ctx.op.insn_type == InternalOp.OP_CMP)):
+        add_a = Signal(a.width + 2, reset_less=True)
+        add_b = Signal(a.width + 2, reset_less=True)
+        add_output = Signal(a.width + 2, reset_less=True)
+        with m.If((op.insn_type == InternalOp.OP_ADD) |
+                  (op.insn_type == InternalOp.OP_CMP)):
             # in bit 0, 1+carry_in creates carry into bit 1 and above
-            comb += add_a.eq(Cat(self.i.carry_in, self.i.a, Const(0, 1)))
-            comb += add_b.eq(Cat(Const(1, 1), self.i.b, Const(0, 1)))
+            comb += add_a.eq(Cat(self.i.carry_in, a, Const(0, 1)))
+            comb += add_b.eq(Cat(Const(1, 1), b, Const(0, 1)))
             comb += add_output.eq(add_a + add_b)
 
         ##########################
         # main switch-statement for handling arithmetic operations
 
-        with m.Switch(self.i.ctx.op.insn_type):
+        with m.Switch(op.insn_type):
             #### CMP, CMPL ####
             with m.Case(InternalOp.OP_CMP):
                 # this is supposed to be inverted (b-a, not a-b)
@@ -66,19 +67,19 @@ class ALUMainStage(PipeModBase):
 
             #### exts (sign-extend) ####
             with m.Case(InternalOp.OP_EXTS):
-                with m.If(self.i.ctx.op.data_len == 1):
-                    comb += o.eq(Cat(self.i.a[0:8], Repl(self.i.a[7], 64-8)))
-                with m.If(self.i.ctx.op.data_len == 2):
-                    comb += o.eq(Cat(self.i.a[0:16], Repl(self.i.a[15], 64-16)))
-                with m.If(self.i.ctx.op.data_len == 4):
-                    comb += o.eq(Cat(self.i.a[0:32], Repl(self.i.a[31], 64-32)))
+                with m.If(op.data_len == 1):
+                    comb += o.eq(Cat(a[0:8], Repl(a[7], 64-8)))
+                with m.If(op.data_len == 2):
+                    comb += o.eq(Cat(a[0:16], Repl(a[15], 64-16)))
+                with m.If(op.data_len == 4):
+                    comb += o.eq(Cat(a[0:32], Repl(a[31], 64-32)))
             with m.Case(InternalOp.OP_CMPEQB):
                 eqs = Signal(8, reset_less=True)
                 src1 = Signal(8, reset_less=True)
-                comb += src1.eq(self.i.a[0:8])
+                comb += src1.eq(a[0:8])
                 for i in range(8):
-                    comb += eqs[i].eq(src1 == self.i.b[8*i:8*(i+1)])
-                comb += self.o.cr0.eq(Cat(Const(0, 2), eqs.any(), Const(0, 1)))
+                    comb += eqs[i].eq(src1 == b[8*i:8*(i+1)])
+                comb += cr0.data.eq(Cat(Const(0, 2), eqs.any(), Const(0, 1)))
 
         ###### sticky overflow and context, both pass-through #####