From: Nikos Nikoleris <nikos.nikoleris@arm.com>
Date: Mon, 5 Dec 2016 21:48:28 +0000 (-0500)
Subject: mem: Invalidate a blk when servicing the 1st invalidating target
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9916e4276cf7d5354e8e95c239698ee38a7f8674;p=gem5.git

mem: Invalidate a blk when servicing the 1st invalidating target

Previously an MSHR with one or more invalidating targets would first
service all targets in the MSHR TargetList and then invalidate the
block. As a result any service snooping targets would lookup in the
cache and incorrectly find the block. This patch forces the
invalidation to happen when the first invalidating target is
encountered.

Change-Id: I9df15de24e1d351cd96f5a2c424d9a03d81c2cce
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
---

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index e139b54a2..1a169c8ea 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1393,6 +1393,17 @@ Cache::recvTimingResp(PacketPtr pkt)
                     pkt->payloadDelay;
                 tgt_pkt->req->setExtraData(0);
             } else {
+                // We are about to send a response to a cache above
+                // that asked for an invalidation; we need to
+                // invalidate our copy immediately as the most
+                // up-to-date copy of the block will now be in the
+                // cache above. It will also prevent this cache from
+                // responding (if the block was previously dirty) to
+                // snoops as they should snoop the caches above where
+                // they will get the response from.
+                if (is_invalidate && blk && blk->isValid()) {
+                    invalidateBlock(blk);
+                }
                 // not a cache fill, just forwarding response
                 // responseLatency is the latency of the return path
                 // from lower level cahces/memory to the core.