From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 1 Sep 2014 13:37:56 +0000 (+0200)
Subject: Fixed "test_cell -simlib all"
X-Git-Tag: yosys-0.4~180
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9923762461d2bc0822daef76bf0b58e772045bc8;p=yosys.git

Fixed "test_cell -simlib all"
---

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 09ffa9a68..3c931c813 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -108,12 +108,13 @@ parameter Y_WIDTH = 0;
 
 input [A_WIDTH-1:0] A;
 output [Y_WIDTH-1:0] Y;
+wire [Y_WIDTH-1:0] tmp;
 
 generate
 	if (A_SIGNED) begin:BLOCK1
-		assign Y = -$signed(A);
+		assign tmp = $signed(A), Y = -tmp;
 	end else begin:BLOCK2
-		assign Y = -A;
+		assign tmp = A, Y = -tmp;
 	end
 endgenerate