From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 16 Mar 2015 21:53:05 +0000 (+0100)
Subject: mibuild/xilinx/common: add XilinxDDROutput
X-Git-Tag: 24jan2021_ls180~2099^2~179
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=993059a59cf322126b63f34698be74773f43c664;p=litex.git

mibuild/xilinx/common: add XilinxDDROutput
---

diff --git a/mibuild/xilinx/common.py b/mibuild/xilinx/common.py
index d8afff53..255d592b 100644
--- a/mibuild/xilinx/common.py
+++ b/mibuild/xilinx/common.py
@@ -84,10 +84,24 @@ class XilinxDifferentialOutput:
 	def lower(dr):
 		return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
 
+class XilinxDDROutputImpl(Module):
+	def __init__(self, i1, i2, o, clk):
+		self.specials += Instance("ODDR",
+				p_DDR_CLK_EDGE="SAME_EDGE",
+				i_C=clk, i_CE=1, i_S=0, i_R=0,
+				i_D1=i1, i_D2=i2, o_Q=o,
+		)
+
+class XilinxDDROutput:
+	@staticmethod
+	def lower(dr):
+		return XilinxDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
+
 xilinx_special_overrides = {
 	NoRetiming:					XilinxNoRetiming,
 	MultiReg:					XilinxMultiReg,
 	AsyncResetSynchronizer:		XilinxAsyncResetSynchronizer,
 	DifferentialInput:			XilinxDifferentialInput,
 	DifferentialOutput:			XilinxDifferentialOutput,
+	DDROutput:					XilinxDDROutput
 }