From: Eddie Hung Date: Tue, 17 Dec 2019 05:48:02 +0000 (-0800) Subject: Merge pull request #1521 from dh73/diego/memattr X-Git-Tag: working-ls180~922 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9935370ada858da56b5d61a3806768af11565a47;p=yosys.git Merge pull request #1521 from dh73/diego/memattr Adding support for Xilinx memory attribute 'block' in single port mode. --- 9935370ada858da56b5d61a3806768af11565a47