From: Richard Sandiford Date: Wed, 14 Aug 2019 08:34:12 +0000 (+0000) Subject: [AArch64] Use unspecs for SVE conversions involving floats X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99361551624427aebe7a856a4327e083aa33733a;p=gcc.git [AArch64] Use unspecs for SVE conversions involving floats This patch changes the SVE FP<->FP and FP<->INT patterns so that they use unspecs rather than rtx codes, continuing the series to make the patterns work with predicates that might not be all-true. 2019-08-14 Richard Sandiford gcc/ * config/aarch64/aarch64.md (UNSPEC_FLOAT_CONVERT): Delete. * config/aarch64/iterators.md (UNSPEC_COND_FCVT, UNSPEC_COND_FCVTZS) (UNSPEC_COND_FCVTZU, UNSPEC_COND_SCVTF, UNSPEC_COND_UCVTF): New unspecs. (optab, su): Handle them. (SVE_COND_FCVTI, SVE_COND_ICVTF): New int iterators. * config/aarch64/aarch64-sve.md (2): Replace with... (2): ...this. (*v16hsf<:SVE_HSDImode>2): Replace with... (*v16hsf2): ...this. (*vnx4sf2): Replace with... (*vnx4sf2): ...this. (*vnx2df2): Replace with... (*vnx2df2): ...this. (vec_pack_fix_trunc_vnx2df): Use SVE_COND_FCVTI instead of FIXUORS. (2): Replace with... (2): ...this. (*vnx8hf2): Replace with... (*vnx8hf2): ...this. (*vnx4sf2): Replace with... (*vnx4sf2): ...this. (aarch64_sve_vnx2df2): Replace with... (aarch64_sve_vnx2df2): ...this. (vec_unpack_float__vnx4si): Pass a GP strictness operand to aarch64_sve_vnx2df2. (vec_pack_trunc_, *trunc2) (aarch64_sve_extend2): Use UNSPEC_COND_FCVT instead of UNSPEC_FLOAT_CONVERT. (vec_unpacks__): Pass a GP strictness operand to aarch64_sve_extend2. From-SVN: r274423 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1dee72251e6..2f2a8a44f6b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,38 @@ +2019-08-14 Richard Sandiford + + * config/aarch64/aarch64.md (UNSPEC_FLOAT_CONVERT): Delete. + * config/aarch64/iterators.md (UNSPEC_COND_FCVT, UNSPEC_COND_FCVTZS) + (UNSPEC_COND_FCVTZU, UNSPEC_COND_SCVTF, UNSPEC_COND_UCVTF): New + unspecs. + (optab, su): Handle them. + (SVE_COND_FCVTI, SVE_COND_ICVTF): New int iterators. + * config/aarch64/aarch64-sve.md + (2): Replace with... + (2): ...this. + (*v16hsf<:SVE_HSDImode>2): Replace with... + (*v16hsf2): ...this. + (*vnx4sf2): Replace with... + (*vnx4sf2): ...this. + (*vnx2df2): Replace with... + (*vnx2df2): ...this. + (vec_pack_fix_trunc_vnx2df): Use SVE_COND_FCVTI instead of + FIXUORS. + (2): Replace with... + (2): ...this. + (*vnx8hf2): Replace with... + (*vnx8hf2): ...this. + (*vnx4sf2): Replace with... + (*vnx4sf2): ...this. + (aarch64_sve_vnx2df2): Replace with... + (aarch64_sve_vnx2df2): ...this. + (vec_unpack_float__vnx4si): Pass a GP strictness + operand to aarch64_sve_vnx2df2. + (vec_pack_trunc_, *trunc2) + (aarch64_sve_extend2): Use UNSPEC_COND_FCVT instead + of UNSPEC_FLOAT_CONVERT. + (vec_unpacks__): Pass a GP strictness operand to + aarch64_sve_extend2. + 2019-08-14 Richard Biener PR target/91154 diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 7cbd690932e..0c9d4c596f9 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3643,13 +3643,13 @@ ;; Unpredicated conversion of floats to integers of the same size (HF to HI, ;; SF to SI or DF to DI). -(define_expand "2" +(define_expand "2" [(set (match_operand: 0 "register_operand") (unspec: [(match_dup 2) - (FIXUORS: - (match_operand:SVE_F 1 "register_operand"))] - UNSPEC_MERGE_PTRUE))] + (const_int SVE_RELAXED_GP) + (match_operand:SVE_F 1 "register_operand")] + SVE_COND_FCVTI))] "TARGET_SVE" { operands[2] = aarch64_ptrue_reg (mode); @@ -3657,37 +3657,37 @@ ) ;; Conversion of SF to DI, SI or HI, predicated with a PTRUE. -(define_insn "*v16hsf2" +(define_insn "*v16hsf2" [(set (match_operand:SVE_HSDI 0 "register_operand" "=w") (unspec:SVE_HSDI [(match_operand: 1 "register_operand" "Upl") - (FIXUORS:SVE_HSDI - (match_operand:VNx8HF 2 "register_operand" "w"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SI 3 "aarch64_sve_gp_strictness") + (match_operand:VNx8HF 2 "register_operand" "w")] + SVE_COND_FCVTI))] "TARGET_SVE" "fcvtz\t%0., %1/m, %2.h" ) ;; Conversion of SF to DI or SI, predicated with a PTRUE. -(define_insn "*vnx4sf2" +(define_insn "*vnx4sf2" [(set (match_operand:SVE_SDI 0 "register_operand" "=w") (unspec:SVE_SDI [(match_operand: 1 "register_operand" "Upl") - (FIXUORS:SVE_SDI - (match_operand:VNx4SF 2 "register_operand" "w"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SI 3 "aarch64_sve_gp_strictness") + (match_operand:VNx4SF 2 "register_operand" "w")] + SVE_COND_FCVTI))] "TARGET_SVE" "fcvtz\t%0., %1/m, %2.s" ) ;; Conversion of DF to DI or SI, predicated with a PTRUE. -(define_insn "*vnx2df2" +(define_insn "*vnx2df2" [(set (match_operand:SVE_SDI 0 "register_operand" "=w") (unspec:SVE_SDI [(match_operand:VNx2BI 1 "register_operand" "Upl") - (FIXUORS:SVE_SDI - (match_operand:VNx2DF 2 "register_operand" "w"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SI 3 "aarch64_sve_gp_strictness") + (match_operand:VNx2DF 2 "register_operand" "w")] + SVE_COND_FCVTI))] "TARGET_SVE" "fcvtz\t%0., %1/m, %2.d" ) @@ -3703,13 +3703,15 @@ [(set (match_dup 4) (unspec:VNx4SI [(match_dup 3) - (FIXUORS:VNx4SI (match_operand:VNx2DF 1 "register_operand"))] - UNSPEC_MERGE_PTRUE)) + (const_int SVE_RELAXED_GP) + (match_operand:VNx2DF 1 "register_operand")] + SVE_COND_FCVTI)) (set (match_dup 5) (unspec:VNx4SI [(match_dup 3) - (FIXUORS:VNx4SI (match_operand:VNx2DF 2 "register_operand"))] - UNSPEC_MERGE_PTRUE)) + (const_int SVE_RELAXED_GP) + (match_operand:VNx2DF 2 "register_operand")] + SVE_COND_FCVTI)) (set (match_operand:VNx4SI 0 "register_operand") (unspec:VNx4SI [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))] "TARGET_SVE" @@ -3740,9 +3742,9 @@ [(set (match_operand:SVE_F 0 "register_operand") (unspec:SVE_F [(match_dup 2) - (FLOATUORS:SVE_F - (match_operand: 1 "register_operand"))] - UNSPEC_MERGE_PTRUE))] + (const_int SVE_RELAXED_GP) + (match_operand: 1 "register_operand")] + SVE_COND_ICVTF))] "TARGET_SVE" { operands[2] = aarch64_ptrue_reg (mode); @@ -3755,11 +3757,11 @@ [(set (match_operand:VNx8HF 0 "register_operand" "=w") (unspec:VNx8HF [(match_operand: 1 "register_operand" "Upl") - (FLOATUORS:VNx8HF - (match_operand:SVE_HSDI 2 "register_operand" "w"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SI 3 "aarch64_sve_gp_strictness") + (match_operand:SVE_HSDI 2 "register_operand" "w")] + SVE_COND_ICVTF))] "TARGET_SVE" - "cvtf\t%0.h, %1/m, %2." + "cvtf\t%0.h, %1/m, %2." ) ;; Conversion of DI or SI to the same number of SFs, predicated with a PTRUE. @@ -3767,11 +3769,11 @@ [(set (match_operand:VNx4SF 0 "register_operand" "=w") (unspec:VNx4SF [(match_operand: 1 "register_operand" "Upl") - (FLOATUORS:VNx4SF - (match_operand:SVE_SDI 2 "register_operand" "w"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SI 3 "aarch64_sve_gp_strictness") + (match_operand:SVE_SDI 2 "register_operand" "w")] + SVE_COND_ICVTF))] "TARGET_SVE" - "cvtf\t%0.s, %1/m, %2." + "cvtf\t%0.s, %1/m, %2." ) ;; Conversion of DI or SI to DF, predicated with a PTRUE. @@ -3779,11 +3781,11 @@ [(set (match_operand:VNx2DF 0 "register_operand" "=w") (unspec:VNx2DF [(match_operand:VNx2BI 1 "register_operand" "Upl") - (FLOATUORS:VNx2DF - (match_operand:SVE_SDI 2 "register_operand" "w"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SI 3 "aarch64_sve_gp_strictness") + (match_operand:SVE_SDI 2 "register_operand" "w")] + SVE_COND_ICVTF))] "TARGET_SVE" - "cvtf\t%0.d, %1/m, %2." + "cvtf\t%0.d, %1/m, %2." ) ;; ------------------------------------------------------------------------- @@ -3818,8 +3820,9 @@ : gen_aarch64_sve_zip1vnx4si) (temp, operands[1], operands[1])); rtx ptrue = aarch64_ptrue_reg (VNx2BImode); - emit_insn (gen_aarch64_sve_vnx4sivnx2df2 (operands[0], - ptrue, temp)); + rtx strictness = gen_int_mode (SVE_RELAXED_GP, SImode); + emit_insn (gen_aarch64_sve_vnx4sivnx2df2 + (operands[0], ptrue, temp, strictness)); DONE; } ) @@ -3837,15 +3840,15 @@ [(set (match_dup 4) (unspec:SVE_HSF [(match_dup 3) - (unspec:SVE_HSF [(match_operand: 1 "register_operand")] - UNSPEC_FLOAT_CONVERT)] - UNSPEC_MERGE_PTRUE)) + (const_int SVE_RELAXED_GP) + (match_operand: 1 "register_operand")] + UNSPEC_COND_FCVT)) (set (match_dup 5) (unspec:SVE_HSF [(match_dup 3) - (unspec:SVE_HSF [(match_operand: 2 "register_operand")] - UNSPEC_FLOAT_CONVERT)] - UNSPEC_MERGE_PTRUE)) + (const_int SVE_RELAXED_GP) + (match_operand: 2 "register_operand")] + UNSPEC_COND_FCVT)) (set (match_operand:SVE_HSF 0 "register_operand") (unspec:SVE_HSF [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))] "TARGET_SVE" @@ -3862,10 +3865,9 @@ [(set (match_operand:SVE_HSF 0 "register_operand" "=w") (unspec:SVE_HSF [(match_operand: 1 "register_operand" "Upl") - (unspec:SVE_HSF - [(match_operand: 2 "register_operand" "w")] - UNSPEC_FLOAT_CONVERT)] - UNSPEC_MERGE_PTRUE))] + (match_operand:SI 3 "aarch64_sve_gp_strictness") + (match_operand: 2 "register_operand" "w")] + UNSPEC_COND_FCVT))] "TARGET_SVE" "fcvt\t%0., %1/m, %2." ) @@ -3896,8 +3898,9 @@ : gen_aarch64_sve_zip1) (temp, operands[1], operands[1])); rtx ptrue = aarch64_ptrue_reg (mode); - emit_insn (gen_aarch64_sve_extend2 (operands[0], - ptrue, temp)); + rtx strictness = gen_int_mode (SVE_RELAXED_GP, SImode); + emit_insn (gen_aarch64_sve_extend2 + (operands[0], ptrue, temp, strictness)); DONE; } ) @@ -3908,10 +3911,9 @@ [(set (match_operand: 0 "register_operand" "=w") (unspec: [(match_operand: 1 "register_operand" "Upl") - (unspec: - [(match_operand:SVE_HSF 2 "register_operand" "w")] - UNSPEC_FLOAT_CONVERT)] - UNSPEC_MERGE_PTRUE))] + (match_operand:SI 3 "aarch64_sve_gp_strictness") + (match_operand:SVE_HSF 2 "register_operand" "w")] + UNSPEC_COND_FCVT))] "TARGET_SVE" "fcvt\t%0., %1/m, %2." ) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index f910166bfba..850c6ada2a5 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -226,7 +226,6 @@ UNSPEC_UNPACKSLO UNSPEC_UNPACKULO UNSPEC_PACK - UNSPEC_FLOAT_CONVERT UNSPEC_WHILE_LO UNSPEC_LDN UNSPEC_STN diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 6bf3638ed1a..05adbba9f16 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -480,6 +480,9 @@ UNSPEC_COND_FCMLT ; Used in aarch64-sve.md. UNSPEC_COND_FCMNE ; Used in aarch64-sve.md. UNSPEC_COND_FCMUO ; Used in aarch64-sve.md. + UNSPEC_COND_FCVT ; Used in aarch64-sve.md. + UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md. + UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md. UNSPEC_COND_FDIV ; Used in aarch64-sve.md. UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md. UNSPEC_COND_FMINNM ; Used in aarch64-sve.md. @@ -498,6 +501,8 @@ UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md. UNSPEC_COND_FSQRT ; Used in aarch64-sve.md. UNSPEC_COND_FSUB ; Used in aarch64-sve.md. + UNSPEC_COND_SCVTF ; Used in aarch64-sve.md. + UNSPEC_COND_UCVTF ; Used in aarch64-sve.md. UNSPEC_LASTB ; Used in aarch64-sve.md. UNSPEC_FCADD90 ; Used in aarch64-simd.md. UNSPEC_FCADD270 ; Used in aarch64-simd.md. @@ -1642,6 +1647,9 @@ UNSPEC_COND_FRINTZ UNSPEC_COND_FSQRT]) +(define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU]) +(define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF]) + (define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD UNSPEC_COND_FDIV UNSPEC_COND_FMAXNM @@ -1715,6 +1723,9 @@ (UNSPEC_FMINV "smin_nan") (UNSPEC_COND_FABS "abs") (UNSPEC_COND_FADD "add") + (UNSPEC_COND_FCVT "fcvt") + (UNSPEC_COND_FCVTZS "fix_trunc") + (UNSPEC_COND_FCVTZU "fixuns_trunc") (UNSPEC_COND_FDIV "div") (UNSPEC_COND_FMAXNM "smax") (UNSPEC_COND_FMINNM "smin") @@ -1732,7 +1743,9 @@ (UNSPEC_COND_FRINTX "rint") (UNSPEC_COND_FRINTZ "btrunc") (UNSPEC_COND_FSQRT "sqrt") - (UNSPEC_COND_FSUB "sub")]) + (UNSPEC_COND_FSUB "sub") + (UNSPEC_COND_SCVTF "float") + (UNSPEC_COND_UCVTF "floatuns")]) (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") (UNSPEC_UMINV "umin") @@ -1773,7 +1786,11 @@ (UNSPEC_UNPACKSLO "s") (UNSPEC_UNPACKULO "u") (UNSPEC_SMUL_HIGHPART "s") - (UNSPEC_UMUL_HIGHPART "u")]) + (UNSPEC_UMUL_HIGHPART "u") + (UNSPEC_COND_FCVTZS "s") + (UNSPEC_COND_FCVTZU "u") + (UNSPEC_COND_SCVTF "s") + (UNSPEC_COND_UCVTF "u")]) (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")