From: Xan <Xan@web>
Date: Wed, 25 Apr 2018 11:38:50 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5521
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9948c0f6db0d0bd9ca77c5285b2c46fcc0c37a6e;p=libreriscv.git

---

diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index f470b2868..c01b4b042 100644
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -20,11 +20,12 @@ Register x 3 -> register operations:
 | ----------------------- | -------------- | -------------- | -- | ----- | ----------- | ------------- |
 | rs3            | func_2 | rs2            | rs1            | 1  | mm    | rd1         | VOP opcode    |
 
-mm values:
-mm = 00 -> use current global saturation or rounding, no mask
-mm = 00 -> force saturation or rounding for this instruction only
-mm = 10 -> use v1 as predicate mask
-mm = 11 -> use ~v1 as predicate mask
+Values for mm field (bits 12:13 above):
+
+* mm = 00 -> use current global saturation or rounding, no mask
+* mm = 00 -> force saturation or rounding for this instruction only
+* mm = 10 -> use v1 as predicate mask
+* mm = 11 -> use ~v1 as predicate mask
 
 ## Register file