From: Mikolaj Wielgus <wielgusmikolaj@gmail.com>
Date: Thu, 23 Dec 2021 01:52:51 +0000 (+0000)
Subject: Give unique names to CRTL-generated modules
X-Git-Tag: sv_maxu_works-initial~610
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9953bf177039844f258e074abd6e7c67f146a32b;p=openpower-isa.git

Give unique names to CRTL-generated modules

test_power_decoder.py now passes.
---

diff --git a/src/openpower/decoder/test/_pyrtl.py b/src/openpower/decoder/test/_pyrtl.py
index 2a241fd0..47bf570e 100644
--- a/src/openpower/decoder/test/_pyrtl.py
+++ b/src/openpower/decoder/test/_pyrtl.py
@@ -457,11 +457,6 @@ class _FragmentCompiler:
             code += "#include \"common.h\"\n"
             code += emitter.flush()
 
-            try:
-                os.mkdir("crtl")
-            except FileExistsError:
-                pass
-
             file = open(f"crtl/{domain_process.name}.c", "w")
             file.write(code)
             file.close()
diff --git a/src/openpower/decoder/test/pysim.py b/src/openpower/decoder/test/pysim.py
index 914dd8e5..9021ad2a 100644
--- a/src/openpower/decoder/test/pysim.py
+++ b/src/openpower/decoder/test/pysim.py
@@ -10,6 +10,8 @@ from openpower.decoder.test._pyrtl import _FragmentCompiler
 from nmigen.sim._pycoro import PyCoroProcess
 from nmigen.sim._pyclock import PyClockProcess
 
+import os
+import shutil
 import importlib
 from cffi import FFI
 
@@ -287,12 +289,24 @@ class _PySimulation:
         self.crtl.clear_pending()
         return converged
 
+
 class PySimEngine(BaseEngine):
+    _crtl_counter = 1
+
     def __init__(self, fragment):
         self._state = _PySimulation()
         self._timeline = self._state.timeline
 
         self._fragment = fragment
+
+        if PySimEngine._crtl_counter == 1:
+            shutil.rmtree("crtl", True)
+
+        try:
+            os.mkdir("crtl")
+        except FileExistsError:
+            pass
+
         self._processes = _FragmentCompiler(self._state)(self._fragment)
 
         cdef_file = open("crtl_template.h")
@@ -315,13 +329,18 @@ class PySimEngine(BaseEngine):
 
         ffibuilder = FFI()
         ffibuilder.cdef(cdef)
-        ffibuilder.set_source("crtl.crtl",
+        ffibuilder.set_source(f"crtl.crtl{PySimEngine._crtl_counter}",
                               cdef,
                               sources=["crtl/common.c"]
                                       + [f"crtl/{process.name}.c" for process in self._processes])
         ffibuilder.compile(verbose=True)
+        
+        self._state.crtl = importlib.import_module(f"crtl.crtl{PySimEngine._crtl_counter}").lib
+
+        # Use a counter to generate unique names for modules, because Python won't reload C
+        # extension modules.
+        PySimEngine._crtl_counter += 1
 
-        self._state.crtl = importlib.import_module(f"crtl.crtl").lib
         for process in self._processes:
             process.crtl = self._state.crtl
             process.run = getattr(process.crtl, f"run_{process.name}")