From: Florent Kermarrec Date: Fri, 23 Jan 2015 11:36:45 +0000 (+0100) Subject: test on hardware and clean up/fix X-Git-Tag: 24jan2021_ls180~2572^2~15 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9960ca010a78c8da4f62575b05594fa154180fff;p=litex.git test on hardware and clean up/fix --- diff --git a/README b/README index f93e35e0..901bb281 100644 --- a/README +++ b/README @@ -101,13 +101,19 @@ devel [AT] lists.m-labs.hk. git clone https://github.com/enjoy-digital/litesata 6. Build and load BIST design (only for KC705 for now): - python3 make.py all + python3 make.py all (-s BISTSoCDevel to add LiteScopeLA) 7. Test design (only for KC705 for now): go to ./test directory and run: python3 bist.py -8. If you only want to build the core and use it with your +8. Visualize Link Layer transactions (if BISTSoCDevel): + go to ./test directory and run: + python3 test_la.py [your_cond] + your_cond can be wr_cmd, id_cmd, rd_resp, ... + (open test_la.py to see all conditions or add yours) + +9. If you only want to build the core and use it with your regular design flow: python3 make.py -t core build-core diff --git a/litesata/frontend/bist.py b/litesata/frontend/bist.py index aa1dbdcd..cd405822 100644 --- a/litesata/frontend/bist.py +++ b/litesata/frontend/bist.py @@ -226,6 +226,7 @@ class LiteSATABISTIdentify(Module): source, sink = user_port.sink, user_port.source self.fsm = fsm = FSM(reset_state="IDLE") + self.submodules += fsm fsm.act("IDLE", self.done.eq(1), If(self.start, @@ -288,4 +289,6 @@ class LiteSATABIST(Module, AutoCSR): generator = LiteSATABISTUnitCSR(generator) checker = LiteSATABISTUnitCSR(checker) identify = LiteSATABISTIdentifyCSR(identify) - self.submodules += generator, checker, identify + self.submodules.generator = generator + self.submodules.checker = checker + self.submodules.identify = identify diff --git a/targets/bist.py b/targets/bist.py index ba7bcf07..9d803149 100644 --- a/targets/bist.py +++ b/targets/bist.py @@ -136,7 +136,6 @@ class BISTSoC(GenSoC, AutoCSR): "sata": 10, } csr_map.update(GenSoC.csr_map) - def __init__(self, platform): clk_freq = 166*1000000 GenSoC.__init__(self, platform, clk_freq) @@ -152,7 +151,7 @@ class BISTSoC(GenSoC, AutoCSR): class BISTSoCDevel(BISTSoC, AutoCSR): csr_map = { - "la": 10 + "la": 20 } csr_map.update(BISTSoC.csr_map) def __init__(self, platform): diff --git a/test/test_la.py b/test/test_la.py new file mode 100644 index 00000000..436bc9e2 --- /dev/null +++ b/test/test_la.py @@ -0,0 +1,69 @@ +import sys +from config import * +from tools import * +from bist import * +from litescope.host.driver import LiteScopeLADriver + +la = LiteScopeLADriver(wb.regs, "la") +identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist") +generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist") +checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist") +wb.open() +regs = wb.regs +### + +trig = "now" +if len(sys.argv) < 2: + print("No trigger condition, triggering immediately!") +else: + trig = sys.argv[1] + +conditions = {} +conditions["now"] = {} +conditions["id_cmd"] = { + "sata_command_tx_sink_stb" : 1, + "sata_command_tx_sink_payload_identify" : 1, +} +conditions["id_resp"] = { + "source_source_payload_data" : primitives["X_RDY"], +} +conditions["wr_cmd"] = { + "sata_command_tx_sink_stb" : 1, + "sata_command_tx_sink_payload_write" : 1, +} +conditions["wr_resp"] = { + "sata_command_rx_source_stb" : 1, + "sata_command_rx_source_payload_write" : 1, +} +conditions["rd_cmd"] = { + "sata_command_tx_sink_stb" : 1, + "sata_command_tx_sink_payload_read" : 1, +} +conditions["rd_resp"] = { + "sata_command_rx_source_stb" : 1, + "sata_command_rx_source_payload_read" : 1, +} + +la.prog_term(port=0, cond=conditions[trig]) +la.prog_sum("term") + +# Trigger / wait / receive +la.trigger(offset=64, length=1024) + +#identify.run(blocking=False) +generator.run(0, 2, 1, 0, blocking=False) +#checker.run(0, 2, 1, 0, blocking=False) +la.wait_done() + +la.read() +la.export("dump.vcd") +### +wb.close() + +f = open("dump_link.txt", "w") +data = link_trace(la, + tx_data_name="sink_sink_payload_data", + rx_data_name="source_source_payload_data" +) +f.write(data) +f.close() diff --git a/test/test_link.py b/test/test_link.py deleted file mode 100644 index dfa7d4c5..00000000 --- a/test/test_link.py +++ /dev/null @@ -1,66 +0,0 @@ -import sys -from config import * -from tools import * -from bist import * -from litescope.host.driver import LiteScopeLADriver - -la = LiteScopeLADriver(wb.regs, "la") -identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist") -generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist") -checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist") -wb.open() -regs = wb.regs -### - -if len(sys.argv) < 2: - print("Need trigger condition!") - sys.exit(0) - -conditions = {} -conditions["wr_cmd"] = { - "sata_command_tx_sink_stb" : 1, - "sata_command_tx_sink_payload_write" : 1, -} -conditions["wr_dma_activate"] = { - "sata_command_rx_source_stb" : 1, - "sata_command_rx_source_payload_write" : 1, -} -conditions["rd_cmd"] = { - "sata_command_tx_sink_stb" : 1, - "sata_command_tx_sink_payload_read" : 1, -} -conditions["rd_data"] = { - "sata_command_rx_source_stb" : 1, - "sata_command_rx_source_payload_read" : 1, -} -conditions["id_cmd"] = { - "sata_command_tx_sink_stb" : 1, - "sata_command_tx_sink_payload_identify" : 1, -} -conditions["id_pio_setup"] = { - "source_source_payload_data" : primitives["X_RDY"], -} - -la.prog_term(port=0, cond=conditions[sys.argv[1]]) -la.prog_sum("term") - -# Trigger / wait / receive -la.trigger(offset=512, length=2000) - -#identify.run() -generator.run(0, 2, 1, 0) -#checker.run(0, 2, 1, 0) -la.wait_done() - -la.read() -la.export("dump.vcd") -### -wb.close() - -f = open("dump_link.txt", "w") -data = link_trace(la, - tx_data_name="sink_sink_payload_data", - rx_data_name="source_source_payload_data" -) -f.write(data) -f.close()