From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 May 2020 19:53:13 +0000 (+0100)
Subject: comments
X-Git-Tag: div_pipeline~1385
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9961ed14d9908adf8cd3db5b109dd4fb4cfec1d5;p=soc.git

comments
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index ca1a9636..e5ae956a 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -292,6 +292,7 @@ class L0CacheBuffer(Elaboratable):
             comb += wrport.en.eq(1)                # enable write
             comb += reset_l.s.eq(1)   # reset mode after 1 cycle
 
+        # after waiting one cycle (reset_l is "sync" mode), reset the port
         with m.If(reset_l.q):
             comb += idx_l.s.eq(1)  # deactivate port-index selector
             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle