From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 27 Oct 2023 10:26:18 +0000 (+0100)
Subject: whitespace
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9967547c3f6723660ee6d4fcb245e8d5a1eeb5a2;p=openpower-isa.git

whitespace
---

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index acdb940c..a82c7100 100644
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -43,9 +43,8 @@ Description:
     Let the effective address (EA) be the sum of the contents of
     register RB shifted by (SH+1), and (RA|0).
 
-    The byte in storage addressed by EA is loaded into
-    RT[56:63]. RT[0:55] are set to 0.
-
+    The byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
 
 Special Registers Altered: