From: lkcl Date: Mon, 8 May 2023 11:19:27 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=996df5409805ffd640fb510f5a0942d3b9bbe1e3;p=libreriscv.git --- diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 7c05649ce..57f5e258c 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -32,7 +32,9 @@ Memory Operations as well. Vectorised Load and Store also presents an extra dimension (literally) which creates scenarios unique to Vector applications, that a Scalar (and -even a SIMD) ISA simply never encounters. SVP64 endeavours to add the +even a SIMD) ISA simply never encounters: not even the complex Addressing +Modes of the 68,000 or S/360 resemble Vector Load/Store. +SVP64 endeavours to add the modes typically found in *all* Scalable Vector ISAs, without changing the behaviour of the underlying Base (Scalar) v3.0B operations in any way. (The sole apparent exception is Post-Increment Mode on LD/ST-update @@ -46,7 +48,7 @@ a number of different modes: * **fixed aka "unit" stride** - contiguous sequence with no gaps * **element strided** - sequential but regularly offset, with gaps * **vector indexed** - vector of base addresses and vector of offsets -* **Speculative fail-first** - where it makes sense to do so +* **Speculative Fault-first** - where it makes sense to do so * **Structure Packing** - covered in SV by [[sv/remap]] and Pack/Unpack Mode. *Despite being constructed from Scalar LD/ST none of these Modes exist @@ -65,9 +67,9 @@ clarification is provided below. A minor complication (caused by the retro-fitting of modern Vector features to a Scalar ISA) is that certain features do not exactly make -sense or are considered a security risk. Fail-first on Vector Indexed +sense or are considered a security risk. Fault-first on Vector Indexed would allow attackers to probe large numbers of pages from userspace, -where strided fail-first (by creating contiguous sequential LDs) does not. +where strided Fault-first (by creating contiguous sequential LDs) does not. In addition, reduce mode makes no sense. Realistically we need an alternative table definition for [[sv/svp64]] `RM.MODE`. The following @@ -75,7 +77,8 @@ modes make sense: * saturation * simple (no augmentation) -* fail-first (where Vector Indexed is banned) +* Fault-first (where Vector Indexed is banned) +* Data-dependent Fail-First (extremely useful for Linked-List pointer-chasing) * Signed Effective Address computation (Vector Indexed only) More than that however it is necessary to fit the usual Vector ISA