From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 27 Nov 2019 03:03:02 +0000 (-0800)
Subject: xaiger: do not promote output wires
X-Git-Tag: working-ls180~881^2^2~127
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99702efabae4005970bdbae4bbb34c39fdd4c46d;p=yosys.git

xaiger: do not promote output wires
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 37ef30522..f17a4c775 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -155,11 +155,6 @@ struct XAigerWriter
 			if (wire->port_input)
 				sigmap.add(wire);
 
-		// promote output wires
-		for (auto wire : module->wires())
-			if (wire->port_output)
-				sigmap.add(wire);
-
 		for (auto wire : module->wires())
 		{
 			if (wire->attributes.count("\\init")) {