From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 5 May 2020 14:51:52 +0000 (+0100)
Subject: add progress counter
X-Git-Tag: ls180-24jan2020~63
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9981b3d83bcc35c1aa47ecd25ed71ef484d776ee;p=ieee754fpu.git

add progress counter
---

diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py
index 56f853c7..ee18ff21 100644
--- a/src/ieee754/cordic/test/test_fp_pipe.py
+++ b/src/ieee754/cordic/test/test_fp_pipe.py
@@ -44,7 +44,12 @@ class SinCosTestCase(FHDLTestCase):
             for i in range(40):
                 yield
         def reader_process():
+            counter = 200
             while True:
+                counter -= 1
+                if counter == 0: # some indication of progress
+                    print (".", sep="", end="", flush=True)
+                    counter = 200
                 yield
                 vld = yield dut.n.valid_o
                 if vld:
@@ -63,6 +68,8 @@ class SinCosTestCase(FHDLTestCase):
                     except StopIteration:
                         break
 
+            print() # newline after end of progress-indicator
+
         sim.add_sync_process(writer_process)
         sim.add_sync_process(reader_process)
         with sim.write_vcd("fp_pipeline.vcd", "fp_pipeline.gtkw", traces=[