From: Ali Saidi Date: Mon, 27 Jul 2009 07:51:01 +0000 (-0700) Subject: ARM: Handle register indexed system calls. X-Git-Tag: Calvin_Submission~194^2~31 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99831ed93821ee8efc3e7a4b6671c5b226d245e2;p=gem5.git ARM: Handle register indexed system calls. --- diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa index 76d584858..f43395c19 100644 --- a/src/arch/arm/isa/decoder.isa +++ b/src/arch/arm/isa/decoder.isa @@ -422,7 +422,10 @@ format DataOp { // ARM System Call (SoftWare Interrupt) 1: swi({{ if (testPredicate(Cpsr, condCode)) { - xc->syscall(IMMED_23_0); + if (IMMED_23_0) + xc->syscall(IMMED_23_0); + else + xc->syscall(R7); } }}); } diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index fa41918c1..6e6eea5a8 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -57,6 +57,7 @@ def operands {{ 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), + 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), #Destination register for load/store double instructions 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc index 7158acfff..c5320c1ab 100644 --- a/src/arch/arm/linux/process.cc +++ b/src/arch/arm/linux/process.cc @@ -448,7 +448,8 @@ ArmLinuxProcess::getDesc(int callnum) // Angel SWI syscalls are unsupported in this release if (callnum == 0x123456) { panic("Attempt to execute an ANGEL_SWI system call (newlib-related)"); - } else if ((callnum & 0x00f00000) == 0x00900000) { + } else if ((callnum & 0x00f00000) == 0x00900000 || + (callnum & 0xf0000) == 0xf0000) { callnum &= 0x000fffff; if ((callnum & 0x0f0000) == 0xf0000) { callnum -= 0x0f0001;