From: Zachary Snow <zach@zachjs.com>
Date: Wed, 23 Dec 2020 00:38:51 +0000 (-0700)
Subject: genrtlil: fix mux2rtlil generated wire signedness
X-Git-Tag: working-ls180~148^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=999eec561752706a8ccb085a692684c745415985;p=yosys.git

genrtlil: fix mux2rtlil generated wire signedness
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 500ccf8c0..b8bfdf65e 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -141,6 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 
 	RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
 	wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column);
+	wire->is_signed = that->is_signed;
 
 	for (auto &attr : that->attributes) {
 		if (attr.second->type != AST_CONSTANT)
diff --git a/tests/various/port_sign_extend.v b/tests/various/port_sign_extend.v
index 055f20ad8..446268268 100644
--- a/tests/various/port_sign_extend.v
+++ b/tests/various/port_sign_extend.v
@@ -24,8 +24,8 @@ module PassThrough(a, b);
 	assign b = a;
 endmodule
 
-module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2);
-	output wire [3:0] o1, o2, o3, o4, o5;
+module act(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2);
+	output wire [3:0] o1, o2, o3, o4, o5, o6;
 
 	// unsigned constant
 	PassThrough pt1(1'b1, o1);
@@ -48,6 +48,10 @@ module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2);
 	wire signed [1:0] tmp5b = 2'b01;
 	PassThrough pt5(tmp5a ^ tmp5b, o5);
 
+	wire signed [2:0] tmp6a = 3'b100;
+	wire signed [2:0] tmp6b = 3'b001;
+	PassThrough pt6(tmp6a ? tmp6a : tmp6b, o6);
+
 	output wire [2:0] yay1, nay1;
 	GeneratorSigned1   os1(yay1);
 	GeneratorUnsigned1 ou1(nay1);
@@ -57,14 +61,15 @@ module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2);
 	GeneratorUnsigned2 ou2(nay2);
 endmodule
 
-module ref(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2);
-	output wire [3:0] o1, o2, o3, o4, o5;
+module ref(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2);
+	output wire [3:0] o1, o2, o3, o4, o5, o6;
 
 	assign o1 = 4'b0001;
 	assign o2 = 4'b0001;
 	assign o3 = 4'b1111;
 	assign o4 = 4'b1111;
 	assign o5 = 4'b1110;
+	assign o6 = 4'b1100;
 
 	output wire [2:0] yay1, nay1;
 	assign yay1 = 3'b111;