From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 23 May 2019 18:32:28 +0000 (-0700)
Subject: Add "min bits" and "min wports" to xilinx dram rules
X-Git-Tag: yosys-0.9~113^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99a3fee8f4a0f89f865ccf5292d5e70d59febd9f;p=yosys.git

Add "min bits" and "min wports" to xilinx dram rules
---

diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt
index e6635d0e2..91632bcee 100644
--- a/techlibs/xilinx/drams.txt
+++ b/techlibs/xilinx/drams.txt
@@ -26,11 +26,15 @@ bram $__XILINX_RAM128X1D
 endbram
 
 match $__XILINX_RAM64X1D
+  min bits 5
+  min wports 1
   make_outreg
   or_next_if_better
 endmatch
 
 match $__XILINX_RAM128X1D
+  min bits 9
+  min wports 1
   make_outreg
 endmatch