From: Andreas Sandberg Date: Tue, 26 Jan 2021 12:37:05 +0000 (+0000) Subject: arch, mem, cpu, systemc: Remove Python 2.7 glue code X-Git-Tag: develop-gem5-snapshot~195 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99a6f42ef7765843c16a64d2f15d703fc252f9e4;p=gem5.git arch, mem, cpu, systemc: Remove Python 2.7 glue code Remove uses of six and from __future__ imports as they are no longer needed. Change-Id: Ib10d01d9398795f46eedeb91a02736f248917b6a Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39758 Reviewed-by: Gabe Black Reviewed-by: Jason Lowe-Power Tested-by: kokoro Maintainer: Bobby R. Bruce --- diff --git a/src/arch/arm/fastmodel/SConscript b/src/arch/arm/fastmodel/SConscript index f5516fa1b..21b3d3caa 100644 --- a/src/arch/arm/fastmodel/SConscript +++ b/src/arch/arm/fastmodel/SConscript @@ -35,7 +35,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function from itertools import cycle Import('*') diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py index 53026c16f..0305a024f 100644 --- a/src/arch/micro_asm.py +++ b/src/arch/micro_asm.py @@ -24,8 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import os import sys import re diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py index e34e06e2f..8bab7b952 100755 --- a/src/arch/micro_asm_test.py +++ b/src/arch/micro_asm_test.py @@ -24,8 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - from micro_asm import MicroAssembler, Combinational_Macroop, Rom_Macroop, Rom class Bah(object): diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index 238fa9310..346f0d686 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -105,8 +105,6 @@ def template MicroFpOpConstructor {{ let {{ - import six - # Make these empty strings so that concatenating onto # them will always work. header_output = "" @@ -199,8 +197,7 @@ let {{ return cls - @six.add_metaclass(FpOpMeta) - class FpUnaryOp(X86Microop): + class FpUnaryOp(X86Microop, metaclass=FpOpMeta): # This class itself doesn't act as a microop abstract = True @@ -235,8 +232,7 @@ let {{ "dataSize" : self.dataSize, "spm" : self.spm} - @six.add_metaclass(FpOpMeta) - class FpBinaryOp(X86Microop): + class FpBinaryOp(X86Microop, metaclass=FpOpMeta): # This class itself doesn't act as a microop abstract = True diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index b46be0345..51310b4ba 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -106,16 +106,12 @@ def template MicroLimmOpConstructor {{ }}; let {{ - import six - if six.PY3: - long = int - class LimmOp(X86Microop): def __init__(self, dest, imm, dataSize="env.dataSize"): self.className = "Limm" self.mnemonic = "limm" self.dest = dest - if isinstance(imm, (int, long)): + if isinstance(imm, int): imm = "ULL(%d)" % imm self.imm = imm self.dataSize = dataSize @@ -145,7 +141,7 @@ let {{ self.className = "Lfpimm" self.mnemonic = "lfpimm" self.dest = dest - if isinstance(imm, (int, long)): + if isinstance(imm, int): imm = "ULL(%d)" % imm elif isinstance(imm, float): imm = "floatToBits64(%.16f)" % imm diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 7e5fd1011..e149d4469 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -202,8 +202,7 @@ let {{ return cls - @six.add_metaclass(MediaOpMeta) - class MediaOp(X86Microop): + class MediaOp(X86Microop, metaclass=MediaOpMeta): # This class itself doesn't act as a microop abstract = True diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index da1f9aeb8..c465dccd7 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -416,8 +416,7 @@ let {{ return cls - @six.add_metaclass(RegOpMeta) - class RegOp(X86Microop): + class RegOp(X86Microop, metaclass=RegOpMeta): # This class itself doesn't act as a microop abstract = True diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 025e985f8..cb4341947 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -38,8 +38,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import sys from m5.SimObject import * diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py index 1329dfbb8..e9003bdf3 100644 --- a/src/cpu/minor/MinorCPU.py +++ b/src/cpu/minor/MinorCPU.py @@ -36,8 +36,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - from m5.defines import buildEnv from m5.params import * from m5.proxy import * diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 111877554..6f48c2b1c 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -36,8 +36,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - from m5.defines import buildEnv from m5.params import * from m5.proxy import * diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py index f60d005ba..3da462c21 100644 --- a/src/cpu/simple/BaseSimpleCPU.py +++ b/src/cpu/simple/BaseSimpleCPU.py @@ -24,8 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - from m5.defines import buildEnv from m5.params import * diff --git a/src/mem/qos/QoSPolicy.py b/src/mem/qos/QoSPolicy.py index 0945cd7a4..6e9e90ecc 100644 --- a/src/mem/qos/QoSPolicy.py +++ b/src/mem/qos/QoSPolicy.py @@ -33,8 +33,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from six import string_types - from m5.SimObject import * from m5.params import * @@ -78,7 +76,7 @@ class QoSFixedPriorityPolicy(QoSPolicy): for prio in self._requestor_priorities: request_port = prio[0] priority = prio[1] - if isinstance(request_port, string_types): + if isinstance(request_port, str): self.getCCObject().initRequestorName( request_port, int(priority)) else: @@ -115,7 +113,7 @@ class QoSPropFairPolicy(QoSPolicy): for prio in self._requestor_scores: request_port = prio[0] score = prio[1] - if isinstance(request_port, string_types): + if isinstance(request_port, str): self.getCCObject().initRequestorName( request_port, float(score)) else: diff --git a/src/mem/slicc/main.py b/src/mem/slicc/main.py index f7f04946d..c3afd2e14 100644 --- a/src/mem/slicc/main.py +++ b/src/mem/slicc/main.py @@ -25,8 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import os import sys diff --git a/src/mem/slicc/util.py b/src/mem/slicc/util.py index 7afa4f88e..ace879e33 100644 --- a/src/mem/slicc/util.py +++ b/src/mem/slicc/util.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from six import string_types - import os import sys @@ -50,7 +47,7 @@ class PairContainer(object): class Location(object): def __init__(self, filename, lineno, no_warning=False): - if not isinstance(filename, string_types): + if not isinstance(filename, str): raise AttributeError( "filename must be a string, found {}".format(type(filename))) if not isinstance(lineno, int): diff --git a/src/systemc/tests/config.py b/src/systemc/tests/config.py index f7af1a558..b19908001 100755 --- a/src/systemc/tests/config.py +++ b/src/systemc/tests/config.py @@ -23,8 +23,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import argparse import m5 import os diff --git a/src/systemc/tests/verify.py b/src/systemc/tests/verify.py index 2c0ebc916..6b4cf5ce7 100755 --- a/src/systemc/tests/verify.py +++ b/src/systemc/tests/verify.py @@ -25,8 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import argparse import collections import difflib @@ -38,7 +36,6 @@ import multiprocessing.pool import os import re import subprocess -import six import sys script_path = os.path.abspath(inspect.getfile(inspect.currentframe())) @@ -110,8 +107,7 @@ class TestPhaseMeta(type): super(TestPhaseMeta, cls).__init__(name, bases, d) -@six.add_metaclass(TestPhaseMeta) -class TestPhaseBase(object): +class TestPhaseBase(object, metaclass=TestPhaseMeta): abstract = True def __init__(self, main_args, *args): diff --git a/src/unittest/genini.py b/src/unittest/genini.py index 2575fc05f..854ce0237 100755 --- a/src/unittest/genini.py +++ b/src/unittest/genini.py @@ -25,8 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import getopt, os, os.path, sys from os.path import join as joinpath, realpath