From: Timur Kristóf <timur.kristof@gmail.com>
Date: Thu, 26 Mar 2020 16:17:38 +0000 (+0100)
Subject: aco: Extract setup_tcs_info to a separate function.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99ad62ff277df284f4e6a460db7f72a463ddedc5;p=mesa.git

aco: Extract setup_tcs_info to a separate function.

Will be required by the workgroup size calculation.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
---

diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index b73e404eb65..75f1f9b4881 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -893,19 +893,8 @@ void setup_gs_variables(isel_context *ctx, nir_shader *nir)
 }
 
 void
-setup_tcs_variables(isel_context *ctx, nir_shader *nir)
+setup_tcs_info(isel_context *ctx, nir_shader *nir)
 {
-   switch (ctx->stage) {
-   case tess_control_hs:
-      ctx->tcs_num_inputs = ctx->args->options->key.tcs.num_inputs;
-      break;
-   case vertex_tess_control_hs:
-      ctx->tcs_num_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
-      break;
-   default:
-      unreachable("Unsupported TCS shader stage");
-   }
-
    /* When the number of TCS input and output vertices are the same (typically 3):
     * - There is an equal amount of LS and HS invocations
     * - In case of merged LSHS shaders, the LS and HS halves of the shader
@@ -915,6 +904,14 @@ setup_tcs_variables(isel_context *ctx, nir_shader *nir)
       ctx->stage == vertex_tess_control_hs &&
       ctx->args->options->key.tcs.input_vertices == nir->info.tess.tcs_vertices_out;
 
+   if (ctx->stage == tess_control_hs) {
+      ctx->tcs_num_inputs = ctx->args->options->key.tcs.num_inputs;
+   } else if (ctx->stage == vertex_tess_control_hs) {
+      ctx->tcs_num_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
+   } else {
+      unreachable("Unsupported TCS shader stage");
+   }
+
    ctx->tcs_num_patches = get_tcs_num_patches(
                              ctx->args->options->key.tcs.input_vertices,
                              nir->info.tess.tcs_vertices_out,
@@ -936,7 +933,11 @@ setup_tcs_variables(isel_context *ctx, nir_shader *nir)
    ctx->args->shader_info->tcs.lds_size = lds_size;
    ctx->program->config->lds_size = (lds_size + ctx->program->lds_alloc_granule - 1) /
                                     ctx->program->lds_alloc_granule;
+}
 
+void
+setup_tcs_variables(isel_context *ctx, nir_shader *nir)
+{
    nir_foreach_variable(variable, &nir->inputs) {
       variable->data.driver_location = shader_io_get_unique_index((gl_varying_slot) variable->data.location) * 4;
    }
@@ -1247,6 +1248,12 @@ setup_isel_context(Program* program,
    ctx.options = args->options;
    ctx.stage = program->stage;
 
+   if (ctx.stage == tess_control_hs) {
+      setup_tcs_info(&ctx, shaders[0]);
+   } else if (ctx.stage == vertex_tess_control_hs) {
+      setup_tcs_info(&ctx, shaders[1]);
+   }
+
    get_io_masks(&ctx, shader_count, shaders);
 
    unsigned scratch_size = 0;