From: Clifford Wolf Date: Tue, 4 Feb 2014 22:00:32 +0000 (+0100) Subject: Fixed detection of init attribute in opt_rmdff X-Git-Tag: yosys-0.2.0~94 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99b9c56da17403152f1bba3ce00c4f34fcb316ce;p=yosys.git Fixed detection of init attribute in opt_rmdff --- diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 02b7f77e7..9a438537c 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -73,7 +73,7 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) assign_map.apply(sig_c); assign_map.apply(sig_r); - bool has_init; + bool has_init = false; RTLIL::Const val_init; for (auto bit : dff_init_map(sig_q).to_sigbit_vector()) { if (bit.wire == NULL)