From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 7 Jul 2012 09:30:27 +0000 (+0200)
Subject: framebuffer: fix FIFO read clocking
X-Git-Tag: 24jan2021_ls180~3108
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99bb70540713867ed33ff1ab42bb9bc42b8af216;p=litex.git

framebuffer: fix FIFO read clocking
---

diff --git a/milkymist/framebuffer/__init__.py b/milkymist/framebuffer/__init__.py
index 0431d648..f38eadbc 100644
--- a/milkymist/framebuffer/__init__.py
+++ b/milkymist/framebuffer/__init__.py
@@ -189,6 +189,7 @@ class FIFO(Actor):
 		return Fragment(
 			[
 				asfifo.ins["read_en"].eq(1),
+				Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"]),
 				
 				self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
 				asfifo.ins["write_en"].eq(self.endpoints["dac"].stb),
@@ -196,8 +197,6 @@ class FIFO(Actor):
 				
 				self.busy.eq(0),
 				asfifo.ins["rst"].eq(0)
-			], [
-				Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"])
 			],
 			instances=[asfifo])
 
diff --git a/verilog/generic/asfifo.v b/verilog/generic/asfifo.v
index 1618964b..0cb1c203 100644
--- a/verilog/generic/asfifo.v
+++ b/verilog/generic/asfifo.v
@@ -10,7 +10,7 @@ module asfifo #(
 	parameter fifo_depth = (1 << address_width)
 ) (
 	/* Read port */
-	output [data_width-1:0] data_out,
+	output reg [data_width-1:0] data_out,
 	output reg empty,
 	input read_en,
 	input clk_read,
@@ -33,7 +33,12 @@ wire set_status, clear_status;
 reg status;
 wire preset_full, preset_empty;
 
-assign data_out = mem[read_index];
+reg [data_width-1:0] data_out0;
+
+always @(posedge clk_read) begin
+	data_out0 <= mem[read_index];
+	data_out <= data_out0;
+end
 
 always @(posedge clk_write) begin
 	if(write_en & !full)