From: Sebastian Perta <sebastian.perta@renesas.com>
Date: Mon, 22 Jan 2018 18:51:28 +0000 (+0000)
Subject: rl78.md: New define_expand "umindi3".
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99cc06ea069ea91ffb2fab663a2a67375d4b0304;p=gcc.git

rl78.md: New define_expand "umindi3".

2018-01-22  Sebastian Perta  <sebastian.perta@renesas.com>

	* config/rl78/rl78.md: New define_expand "umindi3".

2018-01-22  Sebastian Perta  <sebastian.perta@renesas.com>

	* config/rl78/umindi3.S: New assembly file.
	* config/rl78/t-rl78: Added umindi3.S to LIB2ADD.

From-SVN: r256957
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bf8689abb9f..4e47811fc36 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2018-01-22  Sebastian Perta  <sebastian.perta@renesas.com>
+
+	* config/rl78/rl78.md: New define_expand "umindi3".
+
 2018-01-22  Sebastian Perta  <sebastian.perta@renesas.com>
 
 	* config/rl78/rl78.md: New define_expand "smindi3".
diff --git a/gcc/config/rl78/rl78.md b/gcc/config/rl78/rl78.md
index f3201ff53c7..a447f331ed0 100644
--- a/gcc/config/rl78/rl78.md
+++ b/gcc/config/rl78/rl78.md
@@ -719,6 +719,16 @@
    (set_attr "is_g13_muldiv_insn" "yes")]
 )
 
+(define_expand "umindi3"
+ [(set (match_operand:DI          0 "nonimmediate_operand" "")
+	(umin:DI (match_operand:DI 1 "general_operand"      "")
+		 (match_operand:DI    2 "general_operand"      "")))
+   ]
+  "optimize_size"
+  "rl78_emit_libcall (\"__umindi3\", UMIN, DImode, DImode, 3, operands);
+   DONE;"
+)
+
 (define_expand "umaxdi3"
  [(set (match_operand:DI          0 "nonimmediate_operand" "")
 	(umax:DI (match_operand:DI 1 "general_operand"      "")
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 574d585b8ac..dddf837aad3 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-22  Sebastian Perta  <sebastian.perta@renesas.com>
+
+	* config/rl78/umindi3.S: New assembly file.
+	* config/rl78/t-rl78: Added umindi3.S to LIB2ADD.
+
 2018-01-22  Sebastian Perta  <sebastian.perta@renesas.com>
 
 	* config/rl78/smindi3.S: New assembly file.
diff --git a/libgcc/config/rl78/t-rl78 b/libgcc/config/rl78/t-rl78
index 71de3fa6f4f..1e9a029e9f5 100644
--- a/libgcc/config/rl78/t-rl78
+++ b/libgcc/config/rl78/t-rl78
@@ -33,6 +33,7 @@ LIB2ADD = \
 	$(srcdir)/config/rl78/cmpsi2.S \
 	$(srcdir)/config/rl78/adddi3.S \
 	$(srcdir)/config/rl78/subdi3.S \
+	$(srcdir)/config/rl78/umindi3.S \
 	$(srcdir)/config/rl78/umaxdi3.S \
 	$(srcdir)/config/rl78/smindi3.S \
 	$(srcdir)/config/rl78/smaxdi3.S
diff --git a/libgcc/config/rl78/umindi3.S b/libgcc/config/rl78/umindi3.S
new file mode 100644
index 00000000000..903bbfdab64
--- /dev/null
+++ b/libgcc/config/rl78/umindi3.S
@@ -0,0 +1,74 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+; 
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+; 
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License for more details.
+; 
+; Under Section 7 of GPL version 3, you are granted additional
+; permissions described in the GCC Runtime Library Exception, version
+; 3.1, as published by the Free Software Foundation.
+;
+; You should have received a copy of the GNU General Public License and
+; a copy of the GCC Runtime Library Exception along with this program;
+; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+; <http://www.gnu.org/licenses/>.
+
+
+#include "vregs.h"
+
+    .text
+
+START_FUNC ___umindi3
+
+    ; copy first argument/operand to the output registers
+    movw   ax, [sp+4]
+    movw   r8, ax
+    movw   ax, [sp+6]
+    movw   r10, ax
+    movw   ax, [sp+8]
+    movw   r12, ax
+    movw   ax, [sp+10]
+    movw   r14, ax
+
+    ; use 16-bit compares from the most significant words downto the least significant ones
+    movw   ax, [sp+18]
+    cmpw   ax, r14
+    bc     $.L1
+    bnz    $.L2
+
+    movw   ax, [sp+16]
+    cmpw   ax, r12
+    bc     $.L1
+    bnz    $.L2
+
+    movw   ax, [sp+14]
+    cmpw   ax, r10
+    bc     $.L1
+    bnz    $.L2
+
+    movw   ax, [sp+12]
+    cmpw   ax, r8
+    bc     $.L1
+    ret
+
+.L1:
+    ; copy second argument/operand to the output registers
+    movw   ax, [sp+12]
+    movw   r8, ax
+    movw   ax, [sp+14]
+    movw   r10, ax
+    movw   ax, [sp+16]
+    movw   r12, ax
+    movw   ax, [sp+18]
+    movw   r14, ax
+.L2:
+    ret
+
+END_FUNC ___umindi3