From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 May 2020 22:16:14 +0000 (+0100)
Subject: correct image name
X-Git-Tag: convert-csv-opcode-to-binary~2758
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99cd7e3cee6658cde19376f1c4ac805c3d72bcb5;p=libreriscv.git

correct image name
---

diff --git a/3d_gpu/architecture/6600scoreboard.mdwn b/3d_gpu/architecture/6600scoreboard.mdwn
index b2eca9442..9d7263c8f 100644
--- a/3d_gpu/architecture/6600scoreboard.mdwn
+++ b/3d_gpu/architecture/6600scoreboard.mdwn
@@ -620,7 +620,7 @@ These accumulated signals, coming out on a per-row basis for each
 Operand port, are sent straight to every cell in the corresponding
 FU-FU Matrix row.
 
-[[!img fu_regs_row_pending.png size="600x"]]
+[[!img fu_regs_row_pending_vec.png size="600x"]]
 
 The second vector set accumulates the **column** information.  With the
 FU-Regs Cells capturing the instruction operand read/write register