From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 12:47:52 +0000 (+0200)
Subject: Merge pull request #905 from christian-krieg/feature/python_bindings
X-Git-Tag: yosys-0.9~179
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99d5435650c38fb96dc364c0fd4ac6250a4871ea;p=yosys.git

Merge pull request #905 from christian-krieg/feature/python_bindings

Feature/python bindings
---

99d5435650c38fb96dc364c0fd4ac6250a4871ea
diff --cc kernel/rtlil.cc
index f6f08bb9e,bb870f66f..7e1159cac
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@@ -642,32 -665,19 +668,43 @@@ RTLIL::Module::~Module(
  		delete it->second;
  	for (auto it = processes.begin(); it != processes.end(); ++it)
  		delete it->second;
+ #ifdef WITH_PYTHON
+ 	RTLIL::Module::get_all_modules()->erase(hashidx_);
+ #endif
+ }
+ 
+ #ifdef WITH_PYTHON
+ static std::map<unsigned int, RTLIL::Module*> all_modules;
+ std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
+ {
+ 	return &all_modules;
  }
+ #endif
  
 +void RTLIL::Module::makeblackbox()
 +{
 +	pool<RTLIL::Wire*> delwires;
 +
 +	for (auto it = wires_.begin(); it != wires_.end(); ++it)
 +		if (!it->second->port_input && !it->second->port_output)
 +			delwires.insert(it->second);
 +
 +	for (auto it = memories.begin(); it != memories.end(); ++it)
 +		delete it->second;
 +	memories.clear();
 +
 +	for (auto it = cells_.begin(); it != cells_.end(); ++it)
 +		delete it->second;
 +	cells_.clear();
 +
 +	for (auto it = processes.begin(); it != processes.end(); ++it)
 +		delete it->second;
 +	processes.clear();
 +
 +	remove(delwires);
 +	set_bool_attribute("\\blackbox");
 +}
 +
  void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
  {
  	log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));