From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 27 Feb 2013 09:36:17 +0000 (+0100)
Subject: Added some additional TODO items
X-Git-Tag: yosys-0.2.0~790
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99d73fe0280ab41a1d6e75ef0b9a0117455838f9;p=yosys.git

Added some additional TODO items
---

diff --git a/README b/README
index 5c8671806..0b450ddce 100644
--- a/README
+++ b/README
@@ -153,9 +153,9 @@ for them:
 
 - The "tri", "triand", "trior", "wand" and "wor" net types
 
-- The "library" and "configuration" source file formats 
+- The "config" keyword and library map files
 
-- The "disable" and "primitive" statements
+- The "disable", "primitive" and "specify" statements
 
 - Latched logic (is synthesized as logic with feedback loops)
 
@@ -196,7 +196,11 @@ TODOs / Open Bugs
 - Implement missing Verilog 2005 features:
 
   - Signed constants
+  - Constant functions
+  - Indexed part selects
+  - Multi-dimensional arrays
   - ROM modelling using "initial" blocks
+  - The "defparam <cell_name>.<parameter_name> = <value>;" syntax
   - Builtin primitive gates (and, nand, cmos, nmos, pmos, etc..)
   - Ignore what needs to be ignored (e.g. drive and charge strenghts)
   - Check standard vs. implementation to identify missing features