From: Robert Ou Date: Fri, 11 Aug 2017 09:00:33 +0000 (-0700) Subject: recover_reduce: Add driver script for the $reduce_* recover feature X-Git-Tag: yosys-0.8~330^2~1^2~3 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99dad40ed056e33173be4cb24b476ae0ab28edc7;p=yosys.git recover_reduce: Add driver script for the $reduce_* recover feature Conflicts: passes/techmap/Makefile.inc --- diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 51ed356fe..7561369b9 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -17,6 +17,7 @@ OBJS += passes/techmap/iopadmap.o OBJS += passes/techmap/hilomap.o OBJS += passes/techmap/extract.o OBJS += passes/techmap/extract_fa.o +OBJS += passes/techmap/recover_reduce.o OBJS += passes/techmap/recover_reduce_core.o OBJS += passes/techmap/alumacc.o OBJS += passes/techmap/dff2dffe.o diff --git a/passes/techmap/recover_reduce.cpp b/passes/techmap/recover_reduce.cpp new file mode 100644 index 000000000..21ebac532 --- /dev/null +++ b/passes/techmap/recover_reduce.cpp @@ -0,0 +1,100 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2017 Robert Ou + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct RecoverReducePass : public ScriptPass +{ + RecoverReducePass() : ScriptPass("recover_reduce", "recovers $reduce_* from gates") {} + virtual void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" recover_reduce [options]\n"); + log("\n"); + log("recovers $reduce_* from gates\n"); + log("\n"); + log("Reconstructs $reduce_* elements (e.g. larger gates) given a netlist of gates."); + log("This pass is intended to be used as part of a circuit reverse-engineering workflow.\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this command:\n"); + help_script(); + log("\n"); + } + + bool one_pass, no_final_abc; + + virtual void clear_flags() YS_OVERRIDE + { + one_pass = false; + no_final_abc = false; + } + + virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-one_pass") { + one_pass = true; + continue; + } + if (args[argidx] == "-no_final_abc") { + no_final_abc = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + log_header(design, "Executing recover_reduce.\n"); + log_push(); + + run_script(design, "", ""); + + log_pop(); + } + + virtual void script() YS_OVERRIDE + { + if (!one_pass) + { + // Certain structures such as counters seem to work better if we extract only AND + // and then run a general extract pass. + // XXX: Why is that? Does this work in general? + run("abc -g AND"); + run("recover_reduce_core"); + } + run("abc -g AND,OR,XOR"); + run("recover_reduce_core"); + + if (!no_final_abc) + run("abc"); + + run("clean"); + } +} RecoverReducePass; + +PRIVATE_NAMESPACE_END