From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Sep 2022 13:45:41 +0000 (+0100)
Subject: paragraph explaining regs not always accessible for all ops in svp64.mdwn
X-Git-Tag: opf_rfc_ls005_v1~649
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99e27dde2a1a5166bf312d285cd9182b8b9da97c;p=libreriscv.git

paragraph explaining regs not always accessible for all ops in svp64.mdwn
---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index dec1ff763..dae7e7b29 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -524,6 +524,10 @@ The register files are therefore extended:
 * FP is extended from fp0-32 to fp0-fp127
 * CR Fields are extended from CR0-7 to CR0-127
 
+However due to pressure in `RM.EXTRA` not all these registers
+are accessible by all instructions, particularly those with
+a large number of operands (`madd`, `isel`).
+
 In the following tables register numbers are constructed from the
 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
 or EXTRA3 field from the SV Prefix, determined by the specific