From: Luke Kenneth Casson Leighton Date: Sat, 22 May 2021 11:44:49 +0000 (+0000) Subject: re-add 4k sram X-Git-Tag: LS180_RC3~59 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99e875f5403722bfbccc85b49336de5063944723;p=soclayout.git re-add 4k sram --- diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v index a54a773..18a9327 100644 --- a/experiments9/non_generated/full_core_4_4ksram_libresoc.v +++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v @@ -148142,7 +148142,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.jtag" *) (* generator = "nMigen" *) -module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0__dout, wb_dcache_en, wb_icache_en, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, clk); +module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0__dout, wb_sram_en, wb_dcache_en, wb_icache_en, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) wire \$1 ; @@ -149442,6 +149442,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) reg \wb_icache_en$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) + output wb_sram_en; reg wb_sram_en = 1'h1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) reg \wb_sram_en$next ; @@ -156008,6 +156009,14 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_so_ok$next ; assign \$76 = \p_valid_i$75 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + xer_so_ok <= \xer_so_ok$next ; + always @(posedge coresync_clk) + cr_a <= \cr_a$next ; + always @(posedge coresync_clk) + cr_a_ok <= \cr_a_ok$next ; + always @(posedge coresync_clk) + o <= \o$next ; always @(posedge coresync_clk) o_ok <= \o_ok$next ; always @(posedge coresync_clk) @@ -156060,14 +156069,6 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn r_busy <= \r_busy$next ; always @(posedge coresync_clk) xer_so <= \xer_so$next ; - always @(posedge coresync_clk) - xer_so_ok <= \xer_so_ok$next ; - always @(posedge coresync_clk) - cr_a <= \cr_a$next ; - always @(posedge coresync_clk) - cr_a_ok <= \cr_a_ok$next ; - always @(posedge coresync_clk) - o <= \o$next ; \input$50 \input ( .logical_op__SV_Ptype(input_logical_op__SV_Ptype), .\logical_op__SV_Ptype$23 (\input_logical_op__SV_Ptype$47 ), @@ -207049,6 +207050,582 @@ module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); end endmodule +(* \nmigen.hierarchy = "test_issuer.ti.sram4k_0" *) +(* generator = "nMigen" *) +module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *) + reg [8:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *) + reg [63:0] d; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *) + input enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *) + wire [63:0] q; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_0_wb__ack; + reg sram4k_0_wb__ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + reg \sram4k_0_wb__ack$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_0_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_0_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_0_wb__dat_r; + reg [63:0] sram4k_0_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_0_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_0_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_0_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_0_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + reg wb_active; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:45" *) + reg [7:0] we; + assign \$1 = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_0_wb__stb; + always @(posedge clk) + sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ; + spblock_512w64b8w \spblock_512w64b8w_%s ( + .a(a), + .clk(clk), + .d(d), + .q(q), + .we(we) + ); + always @* begin + if (\initial ) begin end + wb_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + wb_active = \$1 ; + endcase + end + always @* begin + if (\initial ) begin end + \sram4k_0_wb__ack$next = sram4k_0_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + \sram4k_0_wb__ack$next = wb_active; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (rst) + 1'h1: + \sram4k_0_wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + a = 9'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + a = sram4k_0_wb__adr; + endcase + endcase + end + always @* begin + if (\initial ) begin end + sram4k_0_wb__dat_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + sram4k_0_wb__dat_r = q; + endcase + endcase + end + always @* begin + if (\initial ) begin end + d = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + d = sram4k_0_wb__dat_w; + endcase + endcase + end + always @* begin + if (\initial ) begin end + we = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" *) + casez (sram4k_0_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" */ + 1'h1: + we = sram4k_0_wb__sel; + endcase + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.sram4k_1" *) +(* generator = "nMigen" *) +module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *) + reg [8:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *) + reg [63:0] d; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *) + input enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *) + wire [63:0] q; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_1_wb__ack; + reg sram4k_1_wb__ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + reg \sram4k_1_wb__ack$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_1_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_1_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_1_wb__dat_r; + reg [63:0] sram4k_1_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_1_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_1_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_1_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_1_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + reg wb_active; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:45" *) + reg [7:0] we; + assign \$1 = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_1_wb__stb; + always @(posedge clk) + sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ; + spblock_512w64b8w \spblock_512w64b8w_%s ( + .a(a), + .clk(clk), + .d(d), + .q(q), + .we(we) + ); + always @* begin + if (\initial ) begin end + wb_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + wb_active = \$1 ; + endcase + end + always @* begin + if (\initial ) begin end + \sram4k_1_wb__ack$next = sram4k_1_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + \sram4k_1_wb__ack$next = wb_active; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (rst) + 1'h1: + \sram4k_1_wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + a = 9'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + a = sram4k_1_wb__adr; + endcase + endcase + end + always @* begin + if (\initial ) begin end + sram4k_1_wb__dat_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + sram4k_1_wb__dat_r = q; + endcase + endcase + end + always @* begin + if (\initial ) begin end + d = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + d = sram4k_1_wb__dat_w; + endcase + endcase + end + always @* begin + if (\initial ) begin end + we = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" *) + casez (sram4k_1_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" */ + 1'h1: + we = sram4k_1_wb__sel; + endcase + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.sram4k_2" *) +(* generator = "nMigen" *) +module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *) + reg [8:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *) + reg [63:0] d; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *) + input enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *) + wire [63:0] q; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_2_wb__ack; + reg sram4k_2_wb__ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + reg \sram4k_2_wb__ack$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_2_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_2_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_2_wb__dat_r; + reg [63:0] sram4k_2_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_2_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_2_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_2_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_2_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + reg wb_active; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:45" *) + reg [7:0] we; + assign \$1 = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_2_wb__stb; + always @(posedge clk) + sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ; + spblock_512w64b8w \spblock_512w64b8w_%s ( + .a(a), + .clk(clk), + .d(d), + .q(q), + .we(we) + ); + always @* begin + if (\initial ) begin end + wb_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + wb_active = \$1 ; + endcase + end + always @* begin + if (\initial ) begin end + \sram4k_2_wb__ack$next = sram4k_2_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + \sram4k_2_wb__ack$next = wb_active; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (rst) + 1'h1: + \sram4k_2_wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + a = 9'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + a = sram4k_2_wb__adr; + endcase + endcase + end + always @* begin + if (\initial ) begin end + sram4k_2_wb__dat_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + sram4k_2_wb__dat_r = q; + endcase + endcase + end + always @* begin + if (\initial ) begin end + d = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + d = sram4k_2_wb__dat_w; + endcase + endcase + end + always @* begin + if (\initial ) begin end + we = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" *) + casez (sram4k_2_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" */ + 1'h1: + we = sram4k_2_wb__sel; + endcase + endcase + endcase + end +endmodule + +(* \nmigen.hierarchy = "test_issuer.ti.sram4k_3" *) +(* generator = "nMigen" *) +module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, clk); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *) + reg [8:0] a; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + input clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *) + reg [63:0] d; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *) + input enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *) + wire [63:0] q; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + input rst; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_3_wb__ack; + reg sram4k_3_wb__ack = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + reg \sram4k_3_wb__ack$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_3_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_3_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_3_wb__dat_r; + reg [63:0] sram4k_3_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_3_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_3_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_3_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_3_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) + reg wb_active; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:45" *) + reg [7:0] we; + assign \$1 = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:62" *) sram4k_3_wb__stb; + always @(posedge clk) + sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ; + spblock_512w64b8w \spblock_512w64b8w_%s ( + .a(a), + .clk(clk), + .d(d), + .q(q), + .we(we) + ); + always @* begin + if (\initial ) begin end + wb_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + wb_active = \$1 ; + endcase + end + always @* begin + if (\initial ) begin end + \sram4k_3_wb__ack$next = sram4k_3_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + \sram4k_3_wb__ack$next = wb_active; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (rst) + 1'h1: + \sram4k_3_wb__ack$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + a = 9'h000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + a = sram4k_3_wb__adr; + endcase + endcase + end + always @* begin + if (\initial ) begin end + sram4k_3_wb__dat_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + sram4k_3_wb__dat_r = q; + endcase + endcase + end + always @* begin + if (\initial ) begin end + d = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + d = sram4k_3_wb__dat_w; + endcase + endcase + end + always @* begin + if (\initial ) begin end + we = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" *) + casez (enable) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" *) + casez (wb_active) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:67" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" *) + casez (sram4k_3_wb__we) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:77" */ + 1'h1: + we = sram4k_3_wb__sel; + endcase + endcase + endcase + end +endmodule + (* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.src_l" *) (* generator = "nMigen" *) module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk); @@ -208184,7 +208761,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer" *) (* top = 1 *) (* generator = "nMigen" *) -module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_18_o, pll_ana_o, pc_i); +module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_0_wb__err, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_1_wb__err, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_2_wb__err, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, sram4k_3_wb__err, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_18_o, pll_ana_o, pc_i); (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1236" *) wire [1:0] \$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) @@ -208841,6 +209418,78 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t input sdr_we_n__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output sdr_we_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_0_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_0_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_0_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_0_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_0_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_0_wb__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_0_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_0_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_0_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_1_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_1_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_1_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_1_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_1_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_1_wb__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_1_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_1_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_1_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_2_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_2_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_2_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_2_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_2_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_2_wb__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_2_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_2_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_2_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_3_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_3_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_3_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_3_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_3_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_3_wb__err; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_3_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_3_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_3_wb__we; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) wire ti_coresync_clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *) @@ -209164,7 +209813,39 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t .sdr_ras_n__core__o(sdr_ras_n__core__o), .sdr_ras_n__pad__o(sdr_ras_n__pad__o), .sdr_we_n__core__o(sdr_we_n__core__o), - .sdr_we_n__pad__o(sdr_we_n__pad__o) + .sdr_we_n__pad__o(sdr_we_n__pad__o), + .sram4k_0_wb__ack(sram4k_0_wb__ack), + .sram4k_0_wb__adr(sram4k_0_wb__adr), + .sram4k_0_wb__cyc(sram4k_0_wb__cyc), + .sram4k_0_wb__dat_r(sram4k_0_wb__dat_r), + .sram4k_0_wb__dat_w(sram4k_0_wb__dat_w), + .sram4k_0_wb__sel(sram4k_0_wb__sel), + .sram4k_0_wb__stb(sram4k_0_wb__stb), + .sram4k_0_wb__we(sram4k_0_wb__we), + .sram4k_1_wb__ack(sram4k_1_wb__ack), + .sram4k_1_wb__adr(sram4k_1_wb__adr), + .sram4k_1_wb__cyc(sram4k_1_wb__cyc), + .sram4k_1_wb__dat_r(sram4k_1_wb__dat_r), + .sram4k_1_wb__dat_w(sram4k_1_wb__dat_w), + .sram4k_1_wb__sel(sram4k_1_wb__sel), + .sram4k_1_wb__stb(sram4k_1_wb__stb), + .sram4k_1_wb__we(sram4k_1_wb__we), + .sram4k_2_wb__ack(sram4k_2_wb__ack), + .sram4k_2_wb__adr(sram4k_2_wb__adr), + .sram4k_2_wb__cyc(sram4k_2_wb__cyc), + .sram4k_2_wb__dat_r(sram4k_2_wb__dat_r), + .sram4k_2_wb__dat_w(sram4k_2_wb__dat_w), + .sram4k_2_wb__sel(sram4k_2_wb__sel), + .sram4k_2_wb__stb(sram4k_2_wb__stb), + .sram4k_2_wb__we(sram4k_2_wb__we), + .sram4k_3_wb__ack(sram4k_3_wb__ack), + .sram4k_3_wb__adr(sram4k_3_wb__adr), + .sram4k_3_wb__cyc(sram4k_3_wb__cyc), + .sram4k_3_wb__dat_r(sram4k_3_wb__dat_r), + .sram4k_3_wb__dat_w(sram4k_3_wb__dat_w), + .sram4k_3_wb__sel(sram4k_3_wb__sel), + .sram4k_3_wb__stb(sram4k_3_wb__stb), + .sram4k_3_wb__we(sram4k_3_wb__we) ); wrappll wrappll ( .clk_24_i(wrappll_clk_24_i), @@ -209183,7 +209864,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti" *) (* generator = "nMigen" *) -module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, clk); +module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$100 ; @@ -210931,6 +211612,8 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus output jtag_wb__stb; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) + wire jtag_wb_sram_en; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input mspi0_clk__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) @@ -211303,6 +211986,78 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus input sdr_we_n__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output sdr_we_n__pad__o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *) + wire sram4k_0_enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_0_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_0_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_0_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_0_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_0_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_0_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_0_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_0_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *) + wire sram4k_1_enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_1_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_1_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_1_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_1_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_1_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_1_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_1_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_1_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *) + wire sram4k_2_enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_2_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_2_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_2_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_2_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_2_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_2_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_2_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_2_wb__we; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:20" *) + wire sram4k_3_enable; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output sram4k_3_wb__ack; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [8:0] sram4k_3_wb__adr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_3_wb__cyc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + output [63:0] sram4k_3_wb__dat_r; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [63:0] sram4k_3_wb__dat_w; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input [7:0] sram4k_3_wb__sel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_3_wb__stb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) + input sram4k_3_wb__we; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *) reg sv_changed = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *) @@ -212198,7 +212953,60 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus .sdr_we_n__core__o(sdr_we_n__core__o), .sdr_we_n__pad__o(sdr_we_n__pad__o), .wb_dcache_en(core_wb_dcache_en), - .wb_icache_en(imem_wb_icache_en) + .wb_icache_en(imem_wb_icache_en), + .wb_sram_en(jtag_wb_sram_en) + ); + sram4k_0 sram4k_0 ( + .clk(clk), + .enable(sram4k_0_enable), + .rst(rst), + .sram4k_0_wb__ack(sram4k_0_wb__ack), + .sram4k_0_wb__adr(sram4k_0_wb__adr), + .sram4k_0_wb__cyc(sram4k_0_wb__cyc), + .sram4k_0_wb__dat_r(sram4k_0_wb__dat_r), + .sram4k_0_wb__dat_w(sram4k_0_wb__dat_w), + .sram4k_0_wb__sel(sram4k_0_wb__sel), + .sram4k_0_wb__stb(sram4k_0_wb__stb), + .sram4k_0_wb__we(sram4k_0_wb__we) + ); + sram4k_1 sram4k_1 ( + .clk(clk), + .enable(sram4k_1_enable), + .rst(rst), + .sram4k_1_wb__ack(sram4k_1_wb__ack), + .sram4k_1_wb__adr(sram4k_1_wb__adr), + .sram4k_1_wb__cyc(sram4k_1_wb__cyc), + .sram4k_1_wb__dat_r(sram4k_1_wb__dat_r), + .sram4k_1_wb__dat_w(sram4k_1_wb__dat_w), + .sram4k_1_wb__sel(sram4k_1_wb__sel), + .sram4k_1_wb__stb(sram4k_1_wb__stb), + .sram4k_1_wb__we(sram4k_1_wb__we) + ); + sram4k_2 sram4k_2 ( + .clk(clk), + .enable(sram4k_2_enable), + .rst(rst), + .sram4k_2_wb__ack(sram4k_2_wb__ack), + .sram4k_2_wb__adr(sram4k_2_wb__adr), + .sram4k_2_wb__cyc(sram4k_2_wb__cyc), + .sram4k_2_wb__dat_r(sram4k_2_wb__dat_r), + .sram4k_2_wb__dat_w(sram4k_2_wb__dat_w), + .sram4k_2_wb__sel(sram4k_2_wb__sel), + .sram4k_2_wb__stb(sram4k_2_wb__stb), + .sram4k_2_wb__we(sram4k_2_wb__we) + ); + sram4k_3 sram4k_3 ( + .clk(clk), + .enable(sram4k_3_enable), + .rst(rst), + .sram4k_3_wb__ack(sram4k_3_wb__ack), + .sram4k_3_wb__adr(sram4k_3_wb__adr), + .sram4k_3_wb__cyc(sram4k_3_wb__cyc), + .sram4k_3_wb__dat_r(sram4k_3_wb__dat_r), + .sram4k_3_wb__dat_w(sram4k_3_wb__dat_w), + .sram4k_3_wb__sel(sram4k_3_wb__sel), + .sram4k_3_wb__stb(sram4k_3_wb__stb), + .sram4k_3_wb__we(sram4k_3_wb__we) ); xics_icp xics_icp ( .clk(clk), @@ -212247,6 +213055,16 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \dbg_dmi_req_i$next = 1'h0; endcase end + always @* begin + if (\initial ) begin end + \delay$next = delay; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) + casez (\$25 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" */ + 1'h1: + \delay$next = \$27 [1:0]; + endcase + end always @* begin if (\initial ) begin end \core_core_pc$next = core_core_pc; @@ -212939,6 +213757,15 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus new_tb = \$271 [63:0]; endcase end + always @* begin + if (\initial ) begin end + \dbg_dmi_we_i$next = jtag_dmi0__we_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (rst) + 1'h1: + \dbg_dmi_we_i$next = 1'h0; + endcase + end always @* begin if (\initial ) begin end \dec2_cur_pc$next = dec2_cur_pc; @@ -213017,11 +213844,11 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus end always @* begin if (\initial ) begin end - \dbg_dmi_we_i$next = jtag_dmi0__we_i; + \dbg_dmi_din$next = jtag_dmi0__din; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: - \dbg_dmi_we_i$next = 1'h0; + \dbg_dmi_din$next = 64'h0000000000000000; endcase end always @* begin @@ -213039,15 +213866,6 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \pc_ok_delay$next = 1'h0; endcase end - always @* begin - if (\initial ) begin end - \dbg_dmi_din$next = jtag_dmi0__din; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) - casez (rst) - 1'h1: - \dbg_dmi_din$next = 64'h0000000000000000; - endcase - end always @* begin if (\initial ) begin end pc = 64'h0000000000000000; @@ -213238,6 +214056,15 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus endcase endcase end + always @* begin + if (\initial ) begin end + \jtag_dmi0__ack_o$next = dbg_dmi_ack_o; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (rst) + 1'h1: + \jtag_dmi0__ack_o$next = 1'h0; + endcase + end always @* begin if (\initial ) begin end core_data_i = 64'h0000000000000000; @@ -213347,11 +214174,11 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus end always @* begin if (\initial ) begin end - \jtag_dmi0__ack_o$next = dbg_dmi_ack_o; + \jtag_dmi0__dout$next = dbg_dmi_dout; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: - \jtag_dmi0__ack_o$next = 1'h0; + \jtag_dmi0__dout$next = 64'h0000000000000000; endcase end always @* begin @@ -213415,15 +214242,6 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus endcase endcase end - always @* begin - if (\initial ) begin end - \jtag_dmi0__dout$next = dbg_dmi_dout; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) - casez (rst) - 1'h1: - \jtag_dmi0__dout$next = 64'h0000000000000000; - endcase - end always @* begin if (\initial ) begin end imem_f_valid_i = 1'h0; @@ -214433,16 +215251,6 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus end endcase end - always @* begin - if (\initial ) begin end - \delay$next = delay; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) - casez (\$25 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" */ - 1'h1: - \delay$next = \$27 [1:0]; - endcase - end assign \$27 = \$28 ; assign \$104 = \$105 ; assign \$112 = \$113 ; @@ -214473,6 +215281,10 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus assign ti_rst = \$34 ; assign por_clk = clk; assign { xics_icp_ics_i_pri, xics_icp_ics_i_src } = { xics_ics_icp_o_pri, xics_ics_icp_o_src }; + assign sram4k_3_enable = jtag_wb_sram_en; + assign sram4k_2_enable = jtag_wb_sram_en; + assign sram4k_1_enable = jtag_wb_sram_en; + assign sram4k_0_enable = jtag_wb_sram_en; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0" *) diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v index 871cf53..28d409c 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v @@ -1,23 +1,16 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-22 12:34:49 +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-22 12:44:09 //-------------------------------------------------------------------------------- module ls180( - output wire i2c_scl, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_oe, - input wire [15:0] gpio_i, - output wire [15:0] gpio_o, - output wire [15:0] gpio_oe, output wire spimaster_clk, output wire spimaster_mosi, output wire spimaster_cs_n, input wire spimaster_miso, + input wire [15:0] gpio_i, + output wire [15:0] gpio_o, + output wire [15:0] gpio_oe, input wire uart_tx, input wire uart_rx, - input wire eint_0, - input wire eint_1, - input wire eint_2, output wire [12:0] sdram_a, input wire [15:0] sdram_dq_i, output wire [15:0] sdram_dq_o, @@ -30,6 +23,13 @@ module ls180( output wire [1:0] sdram_ba, output wire [1:0] sdram_dm, output wire sdram_clock, + input wire eint_0, + input wire eint_1, + input wire eint_2, + output wire i2c_scl, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_oe, input wire sys_clk, input wire sys_rst, input wire [1:0] sys_clksel_i, @@ -159,22 +159,15 @@ wire [63:0] libresocsim_libresoc3; wire libresocsim_libresoc_pll_18_o; wire [1:0] libresocsim_libresoc_clk_sel; wire libresocsim_libresoc_pll_ana_o; -wire libresocsim_libresoc_constraintmanager_i2c_scl; -wire libresocsim_libresoc_constraintmanager_i2c_sda_i; -wire libresocsim_libresoc_constraintmanager_i2c_sda_o; -wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; -wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; -reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; -reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; wire libresocsim_libresoc_constraintmanager_spimaster_miso; +wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; -wire libresocsim_libresoc_constraintmanager_eint_0; -wire libresocsim_libresoc_constraintmanager_eint_1; -wire libresocsim_libresoc_constraintmanager_eint_2; reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i; reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; @@ -187,6 +180,13 @@ reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; +wire libresocsim_libresoc_constraintmanager_eint_0; +wire libresocsim_libresoc_constraintmanager_eint_1; +wire libresocsim_libresoc_constraintmanager_eint_2; +wire libresocsim_libresoc_constraintmanager_i2c_scl; +wire libresocsim_libresoc_constraintmanager_i2c_sda_i; +wire libresocsim_libresoc_constraintmanager_i2c_sda_o; +wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] libresocsim_interface0_converted_interface_dat_r;