From: Tobias Platen Date: Sun, 3 Oct 2021 07:37:15 +0000 (+0200) Subject: an extra dcbz parameter in all six places X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99efd42ba1883f7c951ef65b207f4de00a88a748;p=soc.git an extra dcbz parameter in all six places --- diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py index 751d2551..cccb2133 100644 --- a/src/soc/experiment/pi2ls.py +++ b/src/soc/experiment/pi2ls.py @@ -46,7 +46,7 @@ class Pi2LSUI(PortInterfaceBase): self.lsui_busy = Signal() self.valid_l = SRLatch(False, name="valid") - def set_wr_addr(self, m, addr, mask, misalign, msr_pr): + def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): m.d.comb += self.valid_l.s.eq(1) m.d.comb += self.lsui.x_mask_i.eq(mask) m.d.comb += self.lsui.x_addr_i.eq(addr) diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index f9aa37df..7d42b8df 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -173,7 +173,7 @@ class PortInterfaceBase(Elaboratable): def connect_port(self, inport): return self.pi.connect_port(inport) - def set_wr_addr(self, m, addr, mask, misalign, msr_pr): pass + def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): pass def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass def set_wr_data(self, m, data, wen): pass def get_rd_data(self, m): pass @@ -256,17 +256,6 @@ class PortInterfaceBase(Elaboratable): comb += pi.addr_ok_o.eq(1) # acknowledge addr ok sync += adrok_l.s.eq(1) # and pull "ack" latch - # if now in "DCBZ" mode: wait for addr_ok, then send the address out - # to memory, acknowledge address, and send out LD data - #with m.If(dcbz_active.q): - ##comb += Display("dcbz active") - # XXX Please don't do it this way, not without discussion - # the exact same address is required to be set by both - # dcbz and stores, so use the exact same function. - # it would be better to add an extra argument to - # set_wr_addr to indicate "dcbz mode". - #self.___use_wr_addr_instead_set_dcbz_addr(m, pi.addr.data) - # if now in "ST" mode: likewise do the same but with "ST" # to memory, acknowledge address, and send out LD data with m.If(st_active.q): @@ -275,7 +264,8 @@ class PortInterfaceBase(Elaboratable): comb += lenexp.len_i.eq(pi.data_len) comb += lenexp.addr_i.eq(lsbaddr) with m.If(pi.addr.ok): - self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr) + is_dcbz = 0 # fixme + self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr, is_dcbz) with m.If(adrok_l.qn): comb += pi.addr_ok_o.eq(1) # acknowledge addr ok sync += adrok_l.s.eq(1) # and pull "ack" latch diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py index 3dde127f..5ba92684 100644 --- a/src/soc/experiment/test/test_l0_cache_buffer2.py +++ b/src/soc/experiment/test/test_l0_cache_buffer2.py @@ -25,7 +25,7 @@ class TestCachedMemoryPortInterface(PortInterfaceBase): super().__init__(regwid, addrwid) self.ldst = LDSTSplitter(32, 48, 4) - def set_wr_addr(self, m, addr, mask, misalign, msr_pr): + def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): m.d.comb += self.ldst.addr_i.eq(addr) def set_rd_addr(self, m, addr, mask, misalign, msr_pr): diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py index 2f219e63..d93bd594 100644 --- a/src/soc/experiment/test/test_mmu_dcache_pi.py +++ b/src/soc/experiment/test/test_mmu_dcache_pi.py @@ -61,7 +61,7 @@ class TestMicrowattMemoryPortInterface(PortInterfaceBase): self.mmu = mmu self.dcache = dcache - def set_wr_addr(self, m, addr, mask, misalign, msr_pr): + def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): m.d.comb += self.dcache.d_in.addr.eq(addr) m.d.comb += self.mmu.l_in.addr.eq(addr) m.d.comb += self.mmu.l_in.load.eq(0) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index c377a6cd..7400c0ae 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -119,30 +119,14 @@ class LoadStore1(PortInterfaceBase): #self.nia = Signal(64) #self.srr1 = Signal(16) - # XXX please don't do it this way (and ask in future). - # the exact same logic is required for setting store addresses - # as for dcbz addresses, therefore why duplicate code? - # it would be better to add an argument to set_wr_addr to - # specifiy that it requires dcbz mode to be set. - def __please_remove_and_use_set_wr_addr_instead_set_dcbz_addr(self, m, addr): - m.d.comb += self.req.load.eq(0) #not a load operation - m.d.comb += self.req.dcbz.eq(1) - #m.d.comb += self.req.byte_sel.eq(mask) - m.d.comb += self.req.addr.eq(addr) - m.d.comb += Display("set_dcbz_addr %i",addr) - #m.d.comb += self.req.priv_mode.eq(~msr_pr) # not-problem ==> priv - #m.d.comb += self.req.virt_mode.eq(msr_pr) # problem-state ==> virt - #m.d.comb += self.req.align_intr.eq(misalign) - return None - - # XXX please add a dcbz argument to all set_wr_addr functions instead. - def set_wr_addr(self, m, addr, mask, misalign, msr_pr): + def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): m.d.comb += self.req.load.eq(0) # store operation m.d.comb += self.req.byte_sel.eq(mask) m.d.comb += self.req.addr.eq(addr) m.d.comb += self.req.priv_mode.eq(~msr_pr) # not-problem ==> priv m.d.comb += self.req.virt_mode.eq(msr_pr) # problem-state ==> virt m.d.comb += self.req.align_intr.eq(misalign) + m.d.comb += self.req.dcbz.eq(is_dcbz) # option to disable the cache entirely for write if self.disable_cache: