From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 23:08:58 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/eddie/fix1115' into xc7mux
X-Git-Tag: working-ls180~1208^2~134
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=99ff7b5c8c74371841e74d81b7a0d63cd9487e61;p=yosys.git

Merge remote-tracking branch 'origin/eddie/fix1115' into xc7mux
---

99ff7b5c8c74371841e74d81b7a0d63cd9487e61
diff --cc CHANGELOG
index b9582fd63,496a521be..1ab1bc4f2
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -17,14 -17,9 +17,15 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "rename -src"
      - Added "equiv_opt" pass
      - Added "read_aiger" frontend
 +    - Added "shregmap -tech xilinx"
 +    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
      - Extended "muxcover -mux{4,8,16}=<cost>"
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 +    - Added "synth -abc9" (experimental)
 +    - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
  
  
  Yosys 0.7 .. Yosys 0.8