From: Michael Nolan <mtnolan2640@gmail.com>
Date: Thu, 14 May 2020 19:19:58 +0000 (-0400)
Subject: Add patch for cmpb
X-Git-Tag: div_pipeline~1219
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a0fc198a07923aa091d032effebef69df6c8753;p=soc.git

Add patch for cmpb
---

diff --git a/src/soc/decoder/isa/fixedlogical.patch b/src/soc/decoder/isa/fixedlogical.patch
new file mode 100644
index 00000000..57331829
--- /dev/null
+++ b/src/soc/decoder/isa/fixedlogical.patch
@@ -0,0 +1,20 @@
+--- fixedlogical.py.orig	2020-05-14 11:04:21.871367557 -0400
++++ fixedlogical.py	2020-05-14 11:04:28.714770484 -0400
+@@ -188,7 +188,7 @@
+         return (RA,)
+ 
+     @inject()
+-    def op_cmpb(self, RB, RA):
++    def op_cmpb(self, RB, RS, RA):
+         for n in range(0, 7 + 1):
+             if eq(RS[8 * n:8 * n + 7 + 1], RB[8 * n:8 * n + 7 + 1]):
+                 RA[8 * n:8 * n + 7 + 1] = concat(1, repeat=8)
+@@ -493,7 +493,7 @@
+                 form='X',
+                 asmregs=[['RA', 'RS'], '(Rc=1)'])
+     fixedlogical_instrs['cmpb'] = instruction_info(func=op_cmpb,
+-                read_regs=OrderedSet(['RB']),
++                read_regs=OrderedSet(['RB', 'RS']),
+                 uninit_regs=OrderedSet(['RA']), write_regs=OrderedSet(['RA']),
+                 special_regs=OrderedSet(), op_fields=OrderedSet(),
+                 form='X',