From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 11 Sep 2012 07:59:37 +0000 (+0200)
Subject: fhdl: list signals in execution order
X-Git-Tag: 24jan2021_ls180~2099^2~836
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a18a9df3fc842639f0c24d0634f67c6fb8ac3a9;p=litex.git

fhdl: list signals in execution order
---

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 307bf657..6b77840b 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -154,6 +154,7 @@ def _cst(x):
 		return x
 
 class Signal(Value):
+	_counter = 0
 	def __init__(self, bv=BV(), name=None, variable=False, reset=0, name_override=None):
 		assert(isinstance(bv, BV))
 		self.bv = bv
@@ -161,7 +162,9 @@ class Signal(Value):
 		self.reset = Constant(reset, bv)
 		self.name_override = name_override
 		self.backtrace = tracer.trace_back(name)
-	
+		self.order = Signal._counter
+		Signal._counter += 1
+
 	def __len__(self):
 		return self.bv.width
 
diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py
index 90ec62e5..ebecf2bb 100644
--- a/migen/fhdl/tools.py
+++ b/migen/fhdl/tools.py
@@ -130,7 +130,7 @@ def is_variable(node):
 
 def insert_reset(rst, sl):
 	targets = list_targets(sl)
-	resetcode = [t.eq(t.reset) for t in targets]
+	resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.order)]
 	return If(rst, *resetcode).Else(*sl)
 
 def value_bv(v):
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 034ac2c6..8993300e 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -110,7 +110,7 @@ def _printheader(f, ios, name, ns):
 	wires = _list_comb_wires(f) | inst_mem_outs
 	r = "module " + name + "(\n"
 	firstp = True
-	for sig in ios:
+	for sig in sorted(ios, key=lambda x: x.order):
 		if not firstp:
 			r += ",\n"
 		firstp = False
@@ -124,7 +124,7 @@ def _printheader(f, ios, name, ns):
 		else:
 			r += "\tinput " + _printsig(ns, sig)
 	r += "\n);\n\n"
-	for sig in sigs - ios:
+	for sig in sorted(sigs - ios, key=lambda x: x.order):
 		if sig in wires:
 			r += "wire " + _printsig(ns, sig) + ";\n"
 		else:
@@ -238,7 +238,7 @@ def _printinit(f, ios, ns):
 		- list_mem_ios(f, False, True)
 	if signals:
 		r += "initial begin\n"
-		for s in signals:
+		for s in sorted(signals, key=lambda x: x.order):
 			r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset) + ";\n"
 		r += "end\n\n"
 	return r