From: Richard Sandiford Date: Thu, 1 Feb 2018 11:02:52 +0000 (+0000) Subject: [AArch64] Tighten aarch64_secondary_reload condition (PR 83845) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a1b9cb4d6fcf88d68f55b97c7d9d09c5606fed7;p=gcc.git [AArch64] Tighten aarch64_secondary_reload condition (PR 83845) aarch64_secondary_reload enforced a secondary reload via aarch64_sve_reload_be for memory and pseudo registers, but failed to do the same for subregs of pseudo registers. To avoid this and any similar problems, the patch instead tests for things that the move patterns handle directly; if the operand isn't one of those, we should use the reload pattern instead. The patch fixes an ICE in sve/mask_struct_store_3.c for aarch64_be, where the bogus target description was (rightly) causing LRA to cycle. 2018-02-01 Richard Sandiford gcc/ PR tearget/83845 * config/aarch64/aarch64.c (aarch64_secondary_reload): Tighten check for operands that need to go through aarch64_sve_reload_be. Reviewed-by: James Greenhalgh From-SVN: r257285 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b1c56173d59..adaec489e96 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-02-01 Richard Sandiford + + PR tearget/83845 + * config/aarch64/aarch64.c (aarch64_secondary_reload): Tighten + check for operands that need to go through aarch64_sve_reload_be. + 2018-02-01 Jakub Jelinek PR tree-optimization/81661 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 174310c9f1b..656dd7614cf 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -7249,9 +7249,14 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x, machine_mode mode, secondary_reload_info *sri) { + /* Use aarch64_sve_reload_be for SVE reloads that cannot be handled + directly by the *aarch64_sve_mov_be move pattern. See the + comment at the head of aarch64-sve.md for more details about the + big-endian handling. */ if (BYTES_BIG_ENDIAN && reg_class_subset_p (rclass, FP_REGS) - && (MEM_P (x) || (REG_P (x) && !HARD_REGISTER_P (x))) + && !((REG_P (x) && HARD_REGISTER_P (x)) + || aarch64_simd_valid_immediate (x, NULL)) && aarch64_sve_data_mode_p (mode)) { sri->icode = CODE_FOR_aarch64_sve_reload_be;