From: Clifford Wolf Date: Sun, 19 Jan 2014 03:18:22 +0000 (+0100) Subject: Added Verilog parser support for asserts X-Git-Tag: yosys-0.2.0~156 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a1eb45c7517f224a2516ce235fd53d01d9ef908;p=yosys.git Added Verilog parser support for asserts --- diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 201584885..ecc58cf63 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -80,6 +80,7 @@ std::string AST::type2str(AstNodeType type) X(AST_CELLTYPE) X(AST_IDENTIFIER) X(AST_PREFIX) + X(AST_ASSERT) X(AST_FCALL) X(AST_TO_SIGNED) X(AST_TO_UNSIGNED) diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 22853d0f9..6aaa90e86 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -58,6 +58,7 @@ namespace AST AST_CELLTYPE, AST_IDENTIFIER, AST_PREFIX, + AST_ASSERT, AST_FCALL, AST_TO_SIGNED, diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l index 9e606d90f..81167cf4e 100644 --- a/frontends/verilog/lexer.l +++ b/frontends/verilog/lexer.l @@ -113,6 +113,8 @@ namespace VERILOG_FRONTEND { "generate" { return TOK_GENERATE; } "endgenerate" { return TOK_ENDGENERATE; } +"assert"([ \t\r\n]+"property")? { return TOK_ASSERT; } + "input" { return TOK_INPUT; } "output" { return TOK_OUTPUT; } "inout" { return TOK_INOUT; } diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 874482d6e..b0c4db8ae 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -104,7 +104,7 @@ static void free_attr(std::map *al) %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED -%token TOK_POS_INDEXED TOK_NEG_INDEXED +%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT %type wire_type range non_opt_range expr basic_expr concat_list rvalue lvalue lvalue_concat_list %type opt_label tok_prim_wrapper hierarchical_id @@ -366,7 +366,7 @@ module_body: module_body_stmt: task_func_decl | param_decl | localparam_decl | defparam_decl | wire_decl | assign_stmt | cell_stmt | - always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr; + always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert; task_func_decl: TOK_TASK TOK_ID ';' { @@ -748,6 +748,11 @@ opt_label: $$ = NULL; }; +assert: + TOK_ASSERT '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_ASSERT, $3)); + }; + simple_behavioral_stmt: lvalue '=' expr { AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $3); @@ -760,7 +765,7 @@ simple_behavioral_stmt: // this production creates the obligatory if-else shift/reduce conflict behavioral_stmt: - defattr | wire_decl | + defattr | assert | wire_decl | simple_behavioral_stmt ';' | hierarchical_id attr { AstNode *node = new AstNode(AST_TCALL);