From: klehman <klehman9@comcast.net>
Date: Tue, 7 Sep 2021 02:22:12 +0000 (-0400)
Subject: Fixed typo for sraw test
X-Git-Tag: DRAFT_SVP64_0_1~30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a202971d6f5bca64f645e81e6d51779987580c1;p=openpower-isa.git

Fixed typo for sraw test
---

diff --git a/src/openpower/decoder/isa/test_caller_shift_rot.py b/src/openpower/decoder/isa/test_caller_shift_rot.py
index 9cc12e86..4bfa5100 100644
--- a/src/openpower/decoder/isa/test_caller_shift_rot.py
+++ b/src/openpower/decoder/isa/test_caller_shift_rot.py
@@ -93,7 +93,7 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_regs)
             self.assertEqual(sim.gpr(3), SelectableInt(0x123456, 64))
 
-    def test_case_srw_1(self):
+    def test_case_srw_2(self):
         lst = ["sraw 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x82345678  # test the carry