From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 7 May 2021 11:15:48 +0000 (+0100)
Subject: whoops setup of core.sv_pred_sm/dm not indented and under "if svp64_en"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a378df412997cdced01be24d40515ff7be14cdc;p=soc.git

whoops setup of core.sv_pred_sm/dm not indented and under "if svp64_en"
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 0305624c..cd347aad 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -723,10 +723,10 @@ class TestIssuerInternal(Elaboratable):
                             # proceed to Decode
                             m.next = "DECODE_SV"
 
-                    # pass predicate mask bits through to satellite decoders
-                    # TODO: for SIMD this will be *multiple* bits
-                    sync += core.sv_pred_sm.eq(self.srcmask[0])
-                    sync += core.sv_pred_dm.eq(self.dstmask[0])
+                        # pass predicate mask bits through to satellite decoders
+                        # TODO: for SIMD this will be *multiple* bits
+                        sync += core.sv_pred_sm.eq(self.srcmask[0])
+                        sync += core.sv_pred_dm.eq(self.dstmask[0])
 
             # after src/dst step have been updated, we are ready
             # to decode the instruction