From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 23 Jan 2015 08:04:22 +0000 (+0100)
Subject: simplify LiteScopeLA export (use vns from platform on atexit)
X-Git-Tag: 24jan2021_ls180~2575^2~39
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a3e9f86cf3615bb70b4ec307166dcb53fd3e2f9;p=litex.git

simplify LiteScopeLA export (use vns from platform on atexit)
---

diff --git a/README b/README
index 01e297c8..6fc5063f 100644
--- a/README
+++ b/README
@@ -49,6 +49,8 @@ external Rx/Tx pins to be ready to debug or control all your Wishbone peripheral
 [> Possibles improvements
 -------------------------
 - add standardized interfaces (AXI, Avalon-ST)
+- add protocols analyzers
+- add signals injection/generation
 - add storage in DRAM
 - add storage in HDD with LiteSATA core (to be released soon!)
 - add Ethernet Wishbone bridge
diff --git a/litescope/frontend/la.py b/litescope/frontend/la.py
index 7264bfe0..beabcff2 100644
--- a/litescope/frontend/la.py
+++ b/litescope/frontend/la.py
@@ -22,6 +22,8 @@ def _getattr_all(l, attr):
 class LiteScopeLA(Module, AutoCSR):
 	def __init__(self, depth, dat, with_rle=False, clk_domain="sys", pipe=False):
 		self.depth = depth
+		if isinstance(dat, tuple):
+			dat = Cat(*dat)
 		self.with_rle = with_rle
 		self.clk_domain = clk_domain
 		self.pipe = pipe
@@ -85,26 +87,7 @@ class LiteScopeLA(Module, AutoCSR):
 		else:
 			self.comb += sink.connect(recorder.dat_sink)
 
-	def export(self, design, layout, filename):
-		# XXX FIXME
-		class SimAsyncResetSynchronizer(Special):
-			def __init__(self, cd, async_reset):
-				Special.__init__(self)
-				self.cd = cd
-				self.async_reset = async_reset
-
-			def iter_expressions(self):
-				yield self.cd, "clk", SPECIAL_INPUT
-				yield self.cd, "rst", SPECIAL_OUTPUT
-				yield self, "async_reset", SPECIAL_INPUT
-
-			@staticmethod
-			def lower(dr):
-				return Module()
-		so = {
-			AsyncResetSynchronizer:	SimAsyncResetSynchronizer
-		}
-		ret, ns = verilog.convert(design, return_ns=True, special_overrides=so)
+	def export(self, layout, vns, filename):
 		r = ""
 		def format_line(*args):
 			return ",".join(args) + "\n"
@@ -114,5 +97,5 @@ class LiteScopeLA(Module, AutoCSR):
 		r += format_line("config", "with_rle", str(int(self.with_rle)))
 
 		for e in layout:
-			r += format_line("layout", ns.get_name(e), str(flen(e)))
+			r += format_line("layout", vns.get_name(e), str(flen(e)))
 		write_to_file(filename, r)
diff --git a/targets/simple.py b/targets/simple.py
index 240264f3..3aaa8d99 100644
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -1,4 +1,4 @@
-import os
+import os, atexit
 
 from migen.bank import csrgen
 from migen.bus import wishbone, csr
@@ -78,7 +78,7 @@ class LiteScopeSoC(GenSoC, AutoCSR):
 		"la":	11
 	}
 	csr_map.update(GenSoC.csr_map)
-	def __init__(self, platform, export_conf=False):
+	def __init__(self, platform):
 		clk_freq = 50*1000000
 		GenSoC.__init__(self, platform, clk_freq)
 		self.submodules.crg = _CRG(platform.request("clk50"))
@@ -93,14 +93,16 @@ class LiteScopeSoC(GenSoC, AutoCSR):
 			cnt0.eq(cnt0+1),
 			cnt1.eq(cnt1+2)
 		]
-		debug = (
+		self.debug = (
 			cnt0,
 			cnt1
 		)
-		self.submodules.la = LiteScopeLA(depth=512, dat=Cat(*debug))
+		self.submodules.la = LiteScopeLA(512, self.debug)
 		self.la.add_port(LiteScopeTerm)
-		if export_conf:
-			self.la.export(self, debug, "./test/la.csv")
+		atexit.register(self.exit, platform)
 
+	def exit(self, platform):
+		if platform.vns is not None:
+			self.la.export(self.debug, platform.vns, "./test/la.csv")
 
 default_subtarget = LiteScopeSoC