From: Jan Hubicka Date: Tue, 6 Jan 2004 17:31:10 +0000 (+0100) Subject: re PR target/10301 (Side effects of architecture specific flags are not documented.) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a6093882252082def6173b7c072a94a90e4cfa0;p=gcc.git re PR target/10301 (Side effects of architecture specific flags are not documented.) PR target/10301 * config.gcc: Accept opteron and athlon-64 as variants of k8. * i386.c (override_options): Likewise. * invoke.texi (i386 -mtune): Expand documentation. From-SVN: r75476 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 95a1dcfee77..594bd19262d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2004-01-06 Jan Hubicka + + PR target/10301 + * config.gcc: Accept opteron and athlon-64 as variants + of k8. + * i386.c (override_options): Likewise. + * invoke.texi (i386 -mtune): Expand documentation. + 2004-01-06 Kazu Hirata * alias.c: Fix comment typos. diff --git a/gcc/config.gcc b/gcc/config.gcc index b4e750a5d0a..d43eb94eeb5 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2340,7 +2340,7 @@ if test x$with_cpu = x ; then ;; i686-*-* | i786-*-*) case ${target_noncanonical} in - k8-*) + k8-*|opteron-*|athlon_64-*) with_cpu=k8 ;; athlon_xp-*|athlon_mp-*|athlon_4-*) @@ -2513,7 +2513,8 @@ fi | i586 | pentium | pentium-mmx | winchip-c6 | winchip2 \ | c3 | c3-2 | i686 | pentiumpro | pentium2 | pentium3 \ | pentium4 | k6 | k6-2 | k6-3 | athlon | athlon-tbird \ - | athlon-4 | athlon-xp | athlon-mp | k8) + | athlon-4 | athlon-xp | athlon-mp | k8 | opteron \ + | athlon64 | athlon-fx) # OK ;; *) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index be4e542b9de..04ffe7ec3fc 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1111,6 +1111,12 @@ override_options (void) | PTA_3DNOW_A | PTA_SSE}, {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT | PTA_3DNOW_A | PTA_SSE | PTA_SSE2}, + {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT + | PTA_3DNOW_A | PTA_SSE | PTA_SSE2}, + {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT + | PTA_3DNOW_A | PTA_SSE | PTA_SSE2}, + {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT + | PTA_3DNOW_A | PTA_SSE | PTA_SSE2}, }; int const pta_size = ARRAY_SIZE (processor_alias_table); diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c6504c50a19..5c46d143edd 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -8090,19 +8090,56 @@ computers: @opindex mtune Tune to @var{cpu-type} everything applicable about the generated code, except for the ABI and the set of available instructions. The choices for -@var{cpu-type} are @samp{i386}, @samp{i486}, @samp{i586}, @samp{i686}, -@samp{pentium}, @samp{pentium-mmx}, @samp{pentiumpro}, @samp{pentium2}, -@samp{pentium3}, @samp{pentium4}, @samp{k6}, @samp{k6-2}, @samp{k6-3}, -@samp{athlon}, @samp{athlon-tbird}, @samp{athlon-4}, @samp{athlon-xp}, -@samp{athlon-mp}, @samp{winchip-c6}, @samp{winchip2}, @samp{k8}, @samp{c3} -and @samp{c3-2}. +@var{cpu-type} are: +@table @emph +@item i386 +Original Intel's i386 CPU. +@item i486 +Intel's i486 CPU. (No scheduling is implemented for this chip.) +@item i586, pentium +Intel Pentium CPU with no MMX support. +@item pentium-mmx +Intel PentiumMMX CPU based on Pentium core with MMX instruction set support. +@item i686, pentiumpro +Intel PentiumPro CPU. +@item pentium2 +Intel Pentium2 CPU based on PentiumPro core with MMX instruction set support. +@item pentium3 +Intel Pentium3 CPU based on PentiumPro core with MMX and SSE instruction set +support. +@item pentium4 +Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set support. +@item k6 +AMD K6 CPU with MMX instruction set support. +@item k6-2, k6-3 +Improved versions of AMD K6 CPU with MMX and 3dNOW! instruction set support. +@item athlon, athlon-tbird +AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and SSE prefetch instructions +support. +@item athlon-4, athlon-xp, athlon-mp +Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and full SSE +instruction set support. +@item k8, opteron, athlon64, athlon-fx +AMD K8 core based CPUs with x86-64 instruction set support. (This supersets +MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.) +@item winchip-c6 +IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction +set support. +@item winchip2 +IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW! +instruction set support. +@item c3 +Via C3 CPU with MMX and 3dNOW! instruction set support. (No scheduling is +implemented for this chip.) +@item c3-2 +Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is +implemented for this chip.) +@end table. While picking a specific @var{cpu-type} will schedule things appropriately for that particular chip, the compiler will not generate any code that does not run on the i386 without the @option{-march=@var{cpu-type}} option -being used. @samp{i586} is equivalent to @samp{pentium} and @samp{i686} -is equivalent to @samp{pentiumpro}. @samp{k6} and @samp{athlon} are the -AMD chips as opposed to the Intel ones. +being used. @item -march=@var{cpu-type} @opindex march