From: Xan <Xan@web>
Date: Wed, 25 Apr 2018 06:05:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5536
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a66e74ab7bda00fc591c6b08e11fb575e800e76;p=libreriscv.git

---

diff --git a/A_Harmonised_RVV_and_Packed_SIMD.mdwn b/A_Harmonised_RVV_and_Packed_SIMD.mdwn
index fa431f1b8..c5e9ca598 100644
--- a/A_Harmonised_RVV_and_Packed_SIMD.mdwn
+++ b/A_Harmonised_RVV_and_Packed_SIMD.mdwn
@@ -1,6 +1,7 @@
 # Proposal to harmonise RV Vector spec with Andes Packed SIMD ("Harmonised" RVP)
 
 [[Comparative analysis Harmonised RVP vs Andes Packed SIMD ISA proposal]]
+[[Comparison of Harmonised RVP vs Andes Packed SIMD ISA proposal]]
 
 ##### MVL, setvl instruction & VL CSR work as per RV Vector spec.