From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Fri, 19 Nov 2021 11:40:24 +0000 (+0000)
Subject: Edited to use soc imports, not working
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a74c39934753612f79dd8b2a1847ec101d7d453;p=pinmux.git

Edited to use soc imports, not working
---

diff --git a/src/spec/test_jtag_tap_srv.py b/src/spec/test_jtag_tap_srv.py
index d6966d7..1ecbd3b 100644
--- a/src/spec/test_jtag_tap_srv.py
+++ b/src/spec/test_jtag_tap_srv.py
@@ -8,17 +8,17 @@ import sys
 from nmigen import (Module, Signal, Elaboratable, Const)
 from c4m.nmigen.jtag.tap import TAP, IOType
 from c4m.nmigen.jtag.bus import Interface as JTAGInterface
-from dmi import DMIInterface, DBGCore
-from dmi_sim import dmi_sim
+from soc.debug.dmi import DMIInterface, DBGCore
+from soc.debug.test.dmi_sim import dmi_sim
 from jtag import JTAG, resiotypes
-from jtagremote import JTAGServer, JTAGClient
+from soc.debug.test.jtagremote import JTAGServer, JTAGClient
 
-#from soc.bus.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 from nmigen.sim import Simulator, Delay, Settle, Tick
 from nmutil.util import wrap
-from jtagutils import (jtag_read_write_reg,
+from soc.debug.jtagutils import (jtag_read_write_reg,
                        jtag_srv, jtag_set_reset,
                        jtag_set_ir, jtag_set_get_dr)