From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 Aug 2018 06:35:56 +0000 (+0100)
Subject: add SDRAM clock output
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a8190f066f0d66cfb39ded12493ad1a3c15b0b1;p=pinmux.git

add SDRAM clock output
---

diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py
index 58e7c02..ce6ba43 100644
--- a/src/bsv/peripheral_gen/sdram.py
+++ b/src/bsv/peripheral_gen/sdram.py
@@ -35,6 +35,7 @@ class sdram(PBase):
         return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
                 'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
                 'sdrcke': 'ifc_sdram_out.osdr_cke',
+                'sdrclk': 'ifc_sdram_out.osdr_clock',
                 'sdrrasn': 'ifc_sdram_out.osdr_ras_n',
                 'sdrcasn': 'ifc_sdram_out.osdr_cas_n',
                 }.get(pname, '')
diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index 80a5129..00d97e4 100644
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -175,7 +175,7 @@ def sdram1(suffix, bank):
         buspins.append("SDRAD%d+" % i)
     for i in range(2):
         buspins.append("SDRBA%d+" % i)
-    buspins += ['SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+',
+    buspins += ['SDRCLK+', 'SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+',
                 'SDRCSn0+']
     return (buspins, inout)