From: Brian Grayson <b.grayson@samsung.com>
Date: Fri, 9 Mar 2012 20:32:41 +0000 (-0500)
Subject: ARM: Fix branch prediction issue with CB(N)Z instruction
X-Git-Tag: stable_2012_06_28~181
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a9a4a0780865dc722b7564ea1c1bf8bacb4e5ce;p=gem5.git

ARM: Fix branch prediction issue with CB(N)Z instruction
---

diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index 3a8fbb363..6edfb0ee0 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -212,6 +212,8 @@ class %(class_name)s : public %(base_class)s
 };
 }};
 
+// Only used by CBNZ, CBZ which is conditional based on
+// a register value even though the instruction is always unconditional.
 def template BranchImmRegConstructor {{
     inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                           int32_t _imm,
@@ -219,14 +221,7 @@ def template BranchImmRegConstructor {{
         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
     {
         %(constructor)s;
-        if (!(condCode == COND_AL || condCode == COND_UC)) {
-            for (int x = 0; x < _numDestRegs; x++) {
-                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
-            }
-            flags[IsCondControl] = true;
-        } else {
-            flags[IsUncondControl] = true;
-        }
+        flags[IsCondControl] = true;
     }
 }};