From: Andreas Hansson <andreas.hansson@arm.com>
Date: Wed, 18 Sep 2013 12:46:33 +0000 (-0400)
Subject: mem: Fix scheduling bug in SimpleMemory
X-Git-Tag: stable_2014_02_15~125
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9aa939891f9d8250dde552638bb03d3f3b6ba268;p=gem5.git

mem: Fix scheduling bug in SimpleMemory

This patch ensures that a dequeue event is not scheduled if the memory
controller is waiting for a retry already. Without this check it is
possible for the controller to attempt sending something whilst
already having one packet that is in retry, thus causing the bus to
have an assertion failure.
---

diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index 74d5c4ab2..2549cbe39 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -155,7 +155,7 @@ SimpleMemory::recvTimingReq(PacketPtr pkt)
         // the end even if the latency suggests it should be sent
         // before the packet(s) before it
         packetQueue.push_back(DeferredPacket(pkt, curTick() + getLatency()));
-        if (!dequeueEvent.scheduled())
+        if (!retryResp && !dequeueEvent.scheduled())
             schedule(dequeueEvent, packetQueue.back().tick);
     } else {
         pendingDelete.push_back(pkt);