From: lkcl <lkcl@web>
Date: Wed, 23 Jun 2021 10:11:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~728
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9aab9652c10056418f1093356369d506e8eefd2c;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index a196961ea..5994fc46d 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -87,6 +87,14 @@ with the pseudocode below, the immediate can be used to give unit stride or elem
         if (RAupdate.isvec) u++;
         if (RT.isvec) j++;
 
+    # reverses the bitorder up to "width" bits
+    def bitrev(val, width):
+      result = 0
+      for _ in range(width):
+        result = (result << 1) | (val & 1)
+        val >>= 1
+      return result
+
 Indexed LD is:
  
     # format: ldop RT, RA, RB