From: Brandon Potter <brandon.potter@amd.com>
Date: Mon, 15 May 2017 19:03:20 +0000 (-0500)
Subject: syscall_emul, riscv: add override keyword to RISCV Process class
X-Git-Tag: v19.0.0.0~2789
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9aadcc797263fc268fdd9f921ddffa473f56d78a;p=gem5.git

syscall_emul, riscv: add override keyword to RISCV Process class

Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Reviewed-on: https://gem5-review.googlesource.com/3360
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
---

diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index f732a4436..2a27f350e 100644
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -48,17 +48,19 @@ class RiscvProcess : public Process
   protected:
     RiscvProcess(ProcessParams * params, ObjectFile *objFile);
 
-    void initState();
+    void initState() override;
 
     template<class IntType>
     void argsInit(int pageSize);
 
   public:
-    RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+    RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
     /// Explicitly import the otherwise hidden getSyscallArg
     using Process::getSyscallArg;
-    void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
-    void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+    void setSyscallArg(ThreadContext *tc, int i,
+                       RiscvISA::IntReg val) override;
+    void setSyscallReturn(ThreadContext *tc,
+                          SyscallReturn return_value) override;
 
     virtual bool mmapGrowsDown() const override { return false; }
 };