From: Luke Kenneth Casson Leighton Date: Fri, 24 May 2019 16:54:43 +0000 (+0100) Subject: use internal latch qlq value instead of creating a separate sync register X-Git-Tag: div_pipeline~1949 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9aade2ba12aa80e263a43fefe83f5fbbae211793;p=soc.git use internal latch qlq value instead of creating a separate sync register --- diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index fa0ff11a..242c5a43 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -42,10 +42,6 @@ class DepCell(Elaboratable): m = Module() m.submodules.l = l = SRLatch(sync=False) # async latch - # record current version of q in a sync'd register - cq = Signal() # resets to 0 - m.d.sync += cq.eq(l.q) - # reset on go HI, set on dest and issue m.d.comb += l.s.eq(self.issue_i & self.reg_i) m.d.comb += l.r.eq(self.go_i) @@ -54,9 +50,8 @@ class DepCell(Elaboratable): m.d.comb += self.fwd_o.eq((l.q) & self.hazard_i) # & ~self.issue_i) # Register Select. Activated on go read/write and *current* latch set - m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i) - - m.d.comb += self.q_o.eq(cq | l.q) + m.d.comb += self.q_o.eq(l.qlq) + m.d.comb += self.rsel_o.eq(self.q_o & self.go_i) return m diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py index 544c3265..4ac2a6da 100644 --- a/src/scoreboard/fu_dep_cell.py +++ b/src/scoreboard/fu_dep_cell.py @@ -20,16 +20,12 @@ class DepCell(Elaboratable): m = Module() m.submodules.l = l = SRLatch(sync=False) # async latch - # record current version of q in a sync'd register - cq = Signal() # resets to 0 - m.d.sync += cq.eq(l.q) - # reset on go HI, set on dest and issue m.d.comb += l.s.eq(self.issue_i & self.pend_i) m.d.comb += l.r.eq(self.go_i) # wait out - m.d.comb += self.wait_o.eq((cq | l.q) & ~self.issue_i) + m.d.comb += self.wait_o.eq(l.qlq & ~self.issue_i) return m diff --git a/src/scoreboard/shadow.py b/src/scoreboard/shadow.py index c1d77a02..1b8903dc 100644 --- a/src/scoreboard/shadow.py +++ b/src/scoreboard/shadow.py @@ -3,8 +3,6 @@ from nmigen.cli import verilog, rtlil from nmigen import Module, Signal, Cat, Array, Const, Elaboratable, Repl from nmigen.lib.coding import Decoder -from nmutil.latch import SRLatch, latchregister - from scoreboard.shadow_fn import ShadowFn diff --git a/src/scoreboard/shadow_fn.py b/src/scoreboard/shadow_fn.py index b7edf8e9..bb91e312 100644 --- a/src/scoreboard/shadow_fn.py +++ b/src/scoreboard/shadow_fn.py @@ -23,13 +23,10 @@ class ShadowFn(Elaboratable): m = Module() m.submodules.sl = sl = SRLatch(sync=False) - cq = Signal() # resets to 0 - m.d.sync += cq.eq(sl.q) - m.d.comb += sl.s.eq(self.shadow_i & self.issue_i & ~self.s_good_i) m.d.comb += sl.r.eq(self.s_good_i | (self.issue_i & ~self.shadow_i)) - m.d.comb += self.recover_o.eq((cq | sl.q) & self.s_fail_i) - m.d.comb += self.shadow_o.eq((cq | sl.q)) + m.d.comb += self.recover_o.eq(sl.qlq & self.s_fail_i) + m.d.comb += self.shadow_o.eq(sl.qlq) return m