From: lkcl <lkcl@web>
Date: Sat, 18 Jun 2022 13:48:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1708
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9abedf8bb20c11a5a63093de157b7736097a466a;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index bb333141f..7f155b479 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -178,6 +178,19 @@ Additional links:
 
 # Major opcodes summary
 
+Simple-V itself only requires four instructions with 6-bit Minor XO
+(bits 26-31), and the SVP64 Prefix Encoding requires
+25% space of the EXT001 Major Opcode.
+There are **no** Vector Instructions and consequently **no further
+opcode space is required**.
+
+That said: for the target workloads for which Scalable Vectors are typically
+used, the Scalar ISA on which SV critically relies is somewhat anaemic.
+The Libre-SOC Team has therefore been addressing that by developing
+a number of Scalar instructions in specialist areas (Big Integer,
+Cryptography, 3D, Audio/Video, DSP) and it is these which require
+considerable Scalar opcode space.
+
 Please be advised that even though SV is entirely DRAFT status, there
 is considerable concern that because there is not yet any two-way
 day-to-day communication established with the OPF ISA WG, we have