From: John David Anglin Date: Fri, 7 May 2004 03:09:15 +0000 (+0000) Subject: re PR target/15202 ([3.4 only] ICE in reload_cse_simplify_operands, at postreload.c) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9acf97b6e88ca97c3c6d0a2e1591a9c3f7562ecd;p=gcc.git re PR target/15202 ([3.4 only] ICE in reload_cse_simplify_operands, at postreload.c) PR target/15202 * pa.md (movdi, movsi, movhi, movqi): Support move from shift amount register to general register. From-SVN: r81598 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b152eda55f9..c87394fb900 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2004-05-06 John David Anglin + + PR target/15202 + * pa.md (movdi, movsi, movhi, movqi): Support move from shift amount + register to general register. + 2004-05-07 Alan Modra * config/rs6000/rs6000.h (STACK_BOUNDARY): Use 128 bit for either diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 072f60171e9..1f3e2618eb2 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2264,9 +2264,9 @@ (define_insn "" [(set (match_operand:SI 0 "move_dest_operand" - "=r,r,r,r,r,r,Q,!*q,!*f,*f,T") + "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T") (match_operand:SI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))] + "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && !TARGET_SOFT_FLOAT" @@ -2279,12 +2279,13 @@ ldw%M1 %1,%0 stw%M0 %r1,%0 mtsar %r1 + {mfctl|mfctl,w} %%sar,%0 fcpy,sgl %f1,%0 fldw%F1 %1,%0 fstw%F0 %1,%0" - [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore") + [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:SI 0 "indexed_memory_operand" "=R") @@ -2433,9 +2434,9 @@ (define_insn "" [(set (match_operand:SI 0 "move_dest_operand" - "=r,r,r,r,r,r,Q,!*q") + "=r,r,r,r,r,r,Q,!*q,!r") (match_operand:SI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM"))] + "A,r,J,N,K,RQ,rM,!rM,!*q"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && TARGET_SOFT_FLOAT" @@ -2447,10 +2448,11 @@ {zdepi|depwi,z} %Z1,%0 ldw%M1 %1,%0 stw%M0 %r1,%0 - mtsar %r1" - [(set_attr "type" "load,move,move,move,move,load,store,move") + mtsar %r1 + {mfctl|mfctl,w} %%sar,%0" + [(set_attr "type" "load,move,move,move,move,load,store,move,move") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4")]) ;; Load or store with base-register modification. (define_insn "" @@ -2865,9 +2867,9 @@ (define_insn "" [(set (match_operand:HI 0 "move_dest_operand" - "=r,r,r,r,r,Q,!*q,!*f") + "=r,r,r,r,r,Q,!*q,!r,!*f") (match_operand:HI 1 "move_src_operand" - "r,J,N,K,RQ,rM,!rM,!*fM"))] + "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))] "register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode)" "@ @@ -2878,10 +2880,11 @@ ldh%M1 %1,%0 sth%M0 %r1,%0 mtsar %r1 + mfctr %sar,%0 fcpy,sgl %f1,%0" - [(set_attr "type" "move,move,move,shift,load,store,move,fpalu") + [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") @@ -2989,9 +2992,9 @@ (define_insn "" [(set (match_operand:QI 0 "move_dest_operand" - "=r,r,r,r,r,Q,!*q,!*f") + "=r,r,r,r,r,Q,!*q,!r,!*f") (match_operand:QI 1 "move_src_operand" - "r,J,N,K,RQ,rM,!rM,!*fM"))] + "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))] "register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode)" "@ @@ -3002,10 +3005,11 @@ ldb%M1 %1,%0 stb%M0 %r1,%0 mtsar %r1 + {mfctl|mfctl,w} %%sar,%0 fcpy,sgl %f1,%0" - [(set_attr "type" "move,move,move,shift,load,store,move,fpalu") + [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") @@ -3956,9 +3960,9 @@ (define_insn "" [(set (match_operand:DF 0 "move_dest_operand" - "=!*r,*r,*r,*r,*r,Q,!*q,f,f,T") + "=!*r,*r,*r,*r,*r,Q,!*q,!r,f,f,T") (match_operand:DF 1 "move_src_operand" - "!*r,J,N,K,RQ,*rM,!*rM,fM,RT,f"))] + "!*r,J,N,K,RQ,*rM,!*rM,!*q,fM,RT,f"))] "(register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode)) && !TARGET_SOFT_FLOAT && TARGET_64BIT" @@ -3970,12 +3974,13 @@ ldd%M1 %1,%0 std%M0 %r1,%0 mtsar %r1 + {mfctl|mfctl,w} %%sar,%0 fcpy,dbl %f1,%0 fldd%F1 %1,%0 fstd%F0 %1,%0" - [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore") + [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")]) (define_expand "movdi" @@ -4080,9 +4085,9 @@ (define_insn "" [(set (match_operand:DI 0 "move_dest_operand" - "=r,r,r,r,r,r,Q,!*q,!*f,*f,T") + "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T") (match_operand:DI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*fM,RT,*f"))] + "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))] "(register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode)) && !TARGET_SOFT_FLOAT && TARGET_64BIT" @@ -4095,12 +4100,13 @@ ldd%M1 %1,%0 std%M0 %r1,%0 mtsar %r1 + {mfctl|mfctl,w} %%sar,%0 fcpy,dbl %f1,%0 fldd%F1 %1,%0 fstd%F0 %1,%0" - [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore") + [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:DI 0 "indexed_memory_operand" "=R")