From: Andrew Stubbs Date: Wed, 6 Apr 2011 09:52:52 +0000 (+0000) Subject: arm.h (arm_class_likely_spilled_p): Check against LO_REGS only for Thumb-1. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9adc580c20178d9f9924b90a8f6b7ad22da31037;p=gcc.git arm.h (arm_class_likely_spilled_p): Check against LO_REGS only for Thumb-1. 2011-03-06 Andrew Stubbs Julian Brown Mark Shinwell gcc/ * config/arm/arm.h (arm_class_likely_spilled_p): Check against LO_REGS only for Thumb-1. (MODE_BASE_REG_CLASS): Restrict base registers to those which can be used in short instructions when optimising for size on Thumb-2. Co-Authored-By: Julian Brown Co-Authored-By: Mark Shinwell From-SVN: r172032 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a8f86616a65..a747d602a50 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2011-03-06 Andrew Stubbs + Julian Brown + Mark Shinwell + + * config/arm/arm.h (arm_class_likely_spilled_p): Check against + LO_REGS only for Thumb-1. + (MODE_BASE_REG_CLASS): Restrict base registers to those which can + be used in short instructions when optimising for size on Thumb-2. + 2011-04-06 Eric Botcazou * gimple-low.c (lower_gimple_return): When not optimizing, force labels diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 4fee4dafa02..533ad910c8f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -22333,14 +22333,16 @@ arm_preferred_simd_mode (enum machine_mode mode) /* Implement TARGET_CLASS_LIKELY_SPILLED_P. - We need to define this for LO_REGS on thumb. Otherwise we can end up - using r0-r4 for function arguments, r7 for the stack frame and don't - have enough left over to do doubleword arithmetic. */ - + We need to define this for LO_REGS on Thumb-1. Otherwise we can end up + using r0-r4 for function arguments, r7 for the stack frame and don't have + enough left over to do doubleword arithmetic. For Thumb-2 all the + potentially problematic instructions accept high registers so this is not + necessary. Care needs to be taken to avoid adding new Thumb-2 patterns + that require many low registers. */ static bool arm_class_likely_spilled_p (reg_class_t rclass) { - if ((TARGET_THUMB && rclass == LO_REGS) + if ((TARGET_THUMB1 && rclass == LO_REGS) || rclass == CC_REG) return true; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index f302de2158f..580f2ded1fb 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1165,7 +1165,7 @@ enum reg_class when addressing quantities in QI or HI mode; if we don't know the mode, then we must be conservative. */ #define MODE_BASE_REG_CLASS(MODE) \ - (TARGET_32BIT ? CORE_REGS : \ + (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ (((MODE) == SImode) ? BASE_REGS : LO_REGS)) /* For Thumb we can not support SP+reg addressing, so we return LO_REGS