From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 12 Dec 2014 10:22:21 +0000 (+0100)
Subject: transport_tb: add basic test for TX path
X-Git-Tag: 24jan2021_ls180~2572^2~140
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9ae703efbeefd604853fef2f0147a5c410d82b7a;p=litex.git

transport_tb: add basic test for TX path
---

diff --git a/lib/sata/test/Makefile b/lib/sata/test/Makefile
index 3e9abba8..a15250be 100644
--- a/lib/sata/test/Makefile
+++ b/lib/sata/test/Makefile
@@ -20,7 +20,7 @@ link_tb:
 transport_tb:
 	$(CMD) transport_tb.py
 
-all: crc_tb scrambler_tb
+all: crc_tb scrambler_tb link_tb
 
 clean:
 	rm crc scrambler *.vcd
diff --git a/lib/sata/test/bfm.py b/lib/sata/test/bfm.py
index 7b5d8819..1b077055 100644
--- a/lib/sata/test/bfm.py
+++ b/lib/sata/test/bfm.py
@@ -327,6 +327,8 @@ class FIS_DATA(FIS):
 	def __repr__(self):
 		r = "FIS_DATA\n"
 		r += FIS.__repr__(self)
+		for data in self.packet[1:]:
+			r += "%08x\n" %data
 		return r
 
 class FIS_PIO_SETUP_D2H(FIS):
@@ -365,7 +367,7 @@ class TransportLayer(Module):
 		elif fis_type == fis_types["DMA_ACTIVATE_D2H"]:
 			fis = FIS_DMA_ACTIVATE_D2H(packet)
 		elif fis_type == fis_types["DMA_SETUP"]:
-			fis = FIS_SETUP(packet)
+			fis = FIS_DMA_SETUP(packet)
 		elif fis_type == fis_types["DATA"]:
 			fis = FIS_DATA(packet)
 		elif fis_type == fis_types["PIO_SETUP_D2H"]:
diff --git a/lib/sata/test/transport_tb.py b/lib/sata/test/transport_tb.py
index 70104d37..7c39bf92 100644
--- a/lib/sata/test/transport_tb.py
+++ b/lib/sata/test/transport_tb.py
@@ -14,15 +14,39 @@ from lib.sata.test.common import *
 class TB(Module):
 	def __init__(self):
 		self.submodules.bfm = BFM(phy_debug=False,
-				link_random_level=50, transport_debug=True, transport_loopback=True)
+				link_random_level=0, transport_debug=True, transport_loopback=True)
 		self.submodules.link = SATALinkLayer(self.bfm.phy)
 		self.submodules.transport = SATATransportLayer(self.link)
 
-		self.comb += [
-			self.transport.tx.cmd.stb.eq(1),
-			self.transport.tx.cmd.type.eq(fis_types["REG_H2D"]),
-			self.transport.tx.cmd.lba.eq(0x12345678)
-		]
+	def gen_simulation(self, selfp):
+		for i in range(100):
+			yield
+		selfp.transport.tx.cmd.stb = 1
+		selfp.transport.tx.cmd.type = fis_types["REG_H2D"]
+		selfp.transport.tx.cmd.lba = 0x0123456789
+		yield
+		while selfp.transport.tx.cmd.ack == 0:
+			yield
+		selfp.transport.tx.cmd.stb = 1
+		selfp.transport.tx.cmd.type = fis_types["DMA_SETUP"]
+		selfp.transport.tx.cmd.dma_buffer_id = 0x0123456789ABCDEF
+		yield
+		while selfp.transport.tx.cmd.ack == 0:
+			yield
+		selfp.transport.tx.cmd.stb = 1
+		selfp.transport.tx.cmd.type = fis_types["DATA"]
+		yield
+		for i in range(32):
+			selfp.transport.tx.data.stb = 1
+			#selfp.transport.tx.data.sop = (i==0)
+			selfp.transport.tx.data.eop = (i==31)
+			selfp.transport.tx.data.d = i
+			if selfp.transport.tx.data.ack == 1:
+				yield
+			else:
+				while selfp.transport.tx.data.ack == 0:
+					yield
+		selfp.transport.tx.cmd.stb = 0
 
 if __name__ == "__main__":
-	run_simulation(TB(), ncycles=256, vcd_name="my.vcd", keep_files=True)
+	run_simulation(TB(), ncycles=512, vcd_name="my.vcd", keep_files=True)